ZHCSE48B September 2015 – January 2019 ADC31JB68
PRODUCTION DATA.
The ADC core of this device requires foreground calibration to be performed after power-up to achieve full performance. Immediately after power-up, the ADC31JB68 device detects that the supplies and clock are valid, waits for a power-up delay, and then performs a foreground calibration of the ADC core automatically. The power-up delay is 9 × 106 sampling clock cycles or 18 ms at a 500-MSPS sampling rate. The calibration requires approximately 1.0 × 106 sampling clock cycles.
If the system requires that the ADC31JB68 input clock divider value (CLKDIV) is set to 2 or 4, then ADC calibration should be performed manually after CLKDIV has been set to the desired value. Manually calibrating the ADC core is performed by changing to power down mode, returning to normal operation, and monitoring the CAL_DONE bit in the JESD_STATUS register until calibration is complete. As an alternative to monitoring CAL_DONE, the system may wait 1.5 × 106 sampling clock cycles until calibration completes.
When the ADC core enters normal conversion, background calibration monitors the performance of the device and automatically adjusts the core to optimally correct for changes in the operating conditions such as supply and temperature. The background calibration settling time is less than 375 × 106 sampling clock cycles.