ZHCSCX0D January   2014  – October 2017 ADC12J1600 , ADC12J2700

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     旁路 — 频谱响应 ƒS = 2.7GHz，FIN = 1897MHz（–1dBFS 时）
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Internal Characteristics
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Signal Acquisition
      2. 7.3.2 The Analog Inputs
        1. 7.3.2.1 Input Clamp
        2. 7.3.2.2 AC Coupled Input Usage
        3. 7.3.2.3 DC Coupled Input Usage
        4. 7.3.2.4 Handling Single-Ended Input Signals
      3. 7.3.3 Clocking
      4. 7.3.4 Over-Range Function
      5. 7.3.5 ADC Core Features
        1. 7.3.5.1 The Reference Voltage
        2. 7.3.5.2 Common-Mode Voltage Generation
        3. 7.3.5.3 Bias Current Generation
        4. 7.3.5.4 Full Scale Range Adjust
        5. 7.3.5.5 Offset Adjust
        6. 7.3.5.6 Power-Down
        7. 7.3.5.7 Built-In Temperature Monitor Diode
      6. 7.3.6 Digital Down Converter (DDC)
        1. 7.3.6.1 NCO/Mixer
        2. 7.3.6.2 NCO Settings
          1. 7.3.6.2.1 NCO Frequency Phase Selection
          2. 7.3.6.2.2 NCO_0, NCO_1, and NCO_2 (NCO_x)
          3. 7.3.6.2.3 NCO_SEL Bits (2:0)
          4. 7.3.6.2.4 NCO Frequency Setting (Eight Total)
            1. 7.3.6.2.4.1 Basic NCO Frequency-Setting Mode
            2. 7.3.6.2.4.2 Rational NCO Frequency Setting Mode
          5. 7.3.6.2.5 NCO Phase-Offset Setting (Eight Total)
          6. 7.3.6.2.6 Programmable DDC Delay
        3. 7.3.6.3 Decimation Filters
        4. 7.3.6.4 DDC Output Data
        5. 7.3.6.5 Decimation Settings
          1. 7.3.6.5.1 Decimation Factor
          2. 7.3.6.5.2 DDC Gain Boost
      7. 7.3.7 Data Outputs
        1. 7.3.7.1 The Digital Outputs
        2. 7.3.7.2 JESD204B Interface Features and Settings
          1. 7.3.7.2.1  Scrambler Enable
          2. 7.3.7.2.2  Frames Per Multi-Frame (K-1)
          3. 7.3.7.2.3  DDR
          4. 7.3.7.2.4  JESD Enable
          5. 7.3.7.2.5  JESD Test Modes
          6. 7.3.7.2.6  Configurable Pre-Emphasis
          7. 7.3.7.2.7  Serial Output-Data Formatting
          8. 7.3.7.2.8  JESD204B Synchronization Features
          9. 7.3.7.2.9  SYSREF
          10. 7.3.7.2.10 SYNC~
          11. 7.3.7.2.11 Time Stamp
          12. 7.3.7.2.12 Code-Group Synchronization
          13. 7.3.7.2.13 Multiple ADC Synchronization
    4. 7.4 Device Functional Modes
      1. 7.4.1 DDC Bypass Mode
      2. 7.4.2 DDC Modes
      3. 7.4.3 Calibration
        1. 7.4.3.1 Foreground Calibration Mode
        2. 7.4.3.2 Background Calibration Mode
      4. 7.4.4 Timing Calibration Mode
      5. 7.4.5 Test-Pattern Modes
        1. 7.4.5.1 ADC Test-Pattern Mode
        2. 7.4.5.2 Serializer Test-Mode Details
        3. 7.4.5.3 PRBS Test Modes
        4. 7.4.5.4 Ramp Test Mode
        5. 7.4.5.5 Short and Long-Transport Test Mode
        6. 7.4.5.6 D21.5 Test Mode
        7. 7.4.5.7 K28.5 Test Mode
        8. 7.4.5.8 Repeated ILA Test Mode
        9. 7.4.5.9 Modified RPAT Test Mode
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 Streaming Mode
    6. 7.6 Register Map
      1. 7.6.1 Memory Map
      2. 7.6.2 Register Descriptions
        1. 7.6.2.1 Standard SPI-3.0 (0x000 to 0x00F)
          1. Table 40. Standard SPI-3.0 Registers
          2. 7.6.2.1.1  Configuration A Register (address = 0x000) [reset = 0x3C]
            1. Table 41. CFGA Field Descriptions
          3. 7.6.2.1.2  Configuration B Register (address = 0x001) [reset = 0x00]
            1. Table 42. CFGB Field Descriptions
          4. 7.6.2.1.3  Device Configuration Register (address = 0x002) [reset = 0x00]
            1. Table 43. DEVCFG Field Descriptions
          5. 7.6.2.1.4  Chip Type Register (address = 0x003) [reset = 0x03]
            1. Table 44. CHIP_TYPE Field Descriptions
          6. 7.6.2.1.5  Chip Version Register (address = 0x006) [reset = 0x13]
            1. Table 45. CHIP_VERSION Field Descriptions
          7. 7.6.2.1.6  Vendor Identification Register (address = 0x00C to 0x00D) [reset = 0x0451]
            1. Table 46. VENDOR_ID Field Descriptions
        2. 7.6.2.2 User SPI Configuration (0x010 to 0x01F)
          1. 7.6.2.2.1 User SPI Configuration Register (address = 0x010) [reset = 0x00]
            1. Table 48. USR0 Field Descriptions
        3. 7.6.2.3 General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F)
          1. 7.6.2.3.1 Power-On Reset Register (address = 0x021) [reset = 0x00]
            1. Table 50. POR Field Descriptions
          2. 7.6.2.3.2 I/O Gain 0 Register (address = 0x022) [reset = 0x40]
            1. Table 51. IO_GAIN_0 Field Descriptions
          3. 7.6.2.3.3 IO_GAIN_1 Register (address = 0x023) [reset = 0x00]
            1. Table 52. IO_GAIN_1 Field Descriptions
          4. 7.6.2.3.4 I/O Offset 0 Register (address = 0x025) [reset = 0x40]
            1. Table 53. IO_OFFSET_0 Field Descriptions
          5. 7.6.2.3.5 I/O Offset 1 Register (address = 0x026) [reset = 0x00]
            1. Table 54. IO_OFFSET_1 Field Descriptions
        4. 7.6.2.4 Clock (0x030 to 0x03F)
          1. 7.6.2.4.1 Clock Generator Control 0 Register (address = 0x030) [reset = 0xC0]
            1. Table 56. CLKGEN_0 Field Descriptions
          2. 7.6.2.4.2 Clock Generator Status Register (address = 0x031) [reset = 0x07]
            1. Table 57. CLKGEN_1 Field Descriptions
          3. 7.6.2.4.3 Clock Generator Control 2 Register (address = 0x032) [reset = 0x80]
            1. Table 58. CLKGEN_2 Field Descriptions
          4. 7.6.2.4.4 Analog Miscellaneous Register (address = 0x033) [reset = 0xC3]
            1. Table 59. ANA_MISC Field Descriptions
          5. 7.6.2.4.5 Input Clamp Enable Register (address = 0x034) [reset = 0x2F]
            1. Table 60. IN_CL_EN Field Descriptions
        5. 7.6.2.5 Serializer (0x040 to 0x04F)
          1. 7.6.2.5.1 Serializer Configuration Register (address = 0x040) [reset = 0x04]
            1. Table 62. SER_CFG Field Descriptions
        6. 7.6.2.6 ADC Calibration (0x050 to 0x1FF)
          1. 7.6.2.6.1 Calibration Configuration 0 Register (address = 0x050) [reset = 0x06]
            1. Table 64. CAL_CFG0 Field Descriptions
          2. 7.6.2.6.2 Calibration Configuration 1 Register (address = 0x051) [reset = 0xF4]
            1. Table 65. CAL_CFG1 Field Descriptions
          3. 7.6.2.6.3 Calibration Background Control Register (address = 0x057) [reset = 0x10]
            1. Table 66. CAL_BACK Field Descriptions
          4. 7.6.2.6.4 ADC Pattern and Over-Range Enable Register (address = 0x058) [reset = 0x00]
            1. Table 67. ADC_PAT_OVR_EN Field Descriptions
          5. 7.6.2.6.5 Calibration Vectors Register (address = 0x05A) [reset = 0x00]
            1. Table 68. CAL_VECTOR Field Descriptions
          6. 7.6.2.6.6 Calibration Status Register (address = 0x05B) [reset = undefined]
            1. Table 69. CAL_STAT Field Descriptions
          7. 7.6.2.6.7 Timing Calibration Register (address = 0x066) [reset = 0x02]
            1. Table 70. CAL_STAT Field Descriptions
        7. 7.6.2.7 Digital Down Converter and JESD204B (0x200-0x27F)
          1. 7.6.2.7.1  Digital Down-Converter (DDC) Control Register (address = 0x200) [reset = 0x10]
            1. Table 72. DDC_CTRL1 Field Descriptions
          2. 7.6.2.7.2  JESD204B Control 1 Register (address = 0x201) [reset = 0x0F]
            1. Table 73. JESD_CTRL1 Field Descriptions
          3. 7.6.2.7.3  JESD204B Control 2 Register (address = 0x202) [reset = 0x00]
            1. Table 74. JESD_CTRL2 Field Descriptions
          4. 7.6.2.7.4  JESD204B Device ID (DID) Register (address = 0x203) [reset = 0x00]
            1. Table 75. JESD_DID Field Descriptions
          5. 7.6.2.7.5  JESD204B Control 3 Register (address = 0x204) [reset = 0x00]
            1. Table 76. JESD_CTRL3 Field Descriptions
          6. 7.6.2.7.6  JESD204B and System Status Register (address = 0x205) [reset = Undefined]
            1. Table 77. JESD_STATUS Field Descriptions
          7. 7.6.2.7.7  Overrange Threshold 0 Register (address = 0x206) [reset = 0xF2]
            1. Table 78. OVR_T0 Field Descriptions
          8. 7.6.2.7.8  Overrange Threshold 1 Register (address = 0x207) [reset = 0xAB]
            1. Table 79. OVR_T1 Field Descriptions
          9. 7.6.2.7.9  Overrange Period Register (address = 0x208) [reset = 0x00]
            1. Table 80. OVR_N Field Descriptions
          10. 7.6.2.7.10 DDC Configuration Preset Mode Register (address = 0x20C) [reset = 0x00]
            1. Table 81. NCO_MODE Field Descriptions
          11. 7.6.2.7.11 DDC Configuration Preset Select Register (address = 0x20D) [reset = 0x00]
            1. Table 82. NCO_SEL Field Descriptions
          12. 7.6.2.7.12 Rational NCO Reference Divisor Register (address = 0x20E to 0x20F) [reset = 0x0000]
            1. Table 83. NCO_RDIV Field Descriptions
          13. 7.6.2.7.13 NCO Frequency (Preset x) Register (address = see ) [reset = see ]
            1. Table 84. NCO_FREQ_x Field Descriptions
          14. 7.6.2.7.14 NCO Phase (Preset x) Register (address = see ) [reset = see ]
            1. Table 85. NCO_PHASE_x Field Descriptions
          15. 7.6.2.7.15 DDC Delay (Preset x) Register (address = see ) [reset = see ]
            1. Table 86. DDC_DLY_x Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Oscilloscope
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Initialization Set-Up
      1. 8.3.1 JESD204B Startup Sequence
    4. 8.4 Dos and Don'ts
      1. 8.4.1 Common Application Pitfalls
  9. 9 Power Supply Recommendations
    1. 9.1 Supply Voltage
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Management
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 开发支持
      3. 11.1.3 器件命名规则
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 相关链接
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default setting (725 mVPP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 2.7 or 1.6 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical values are at TA = 25°C.(1)(3)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
DYNAMIC PERFORMANCE CHARACTERISTICS
RES ADC core resolution Resolution with no missing codes 12 Bits
INL Integral non-linearity TA = 25°C ±2 LSB
TA = TMIN to TMAX ±3
DNL Differential non-linearity TA = 25°C ±0.25 LSB
TA = TMIN to TMAX ±0.3
Peak NPR Peak noise power ratio 500-kHz tone spacing from 1 MHz to ƒS / 2−1 MHz, DDC bypass mode
25-MHz wide notch at 320 MHz		 46 dB
IMD3 Third-order intermodulation distortion F1 = 2110 MHz at −13 dBFS
F2 = 2170 MHz at −13 dBFS		 –64 dBc
DDC BYPASS MODE, ADC12J2700, ƒ(DEVCLK) = 2.7 GHz
SNR Signal-to-noise ratio, integrated across entire Nyquist bandwidth
Input frequency-dependent interleaving spurs included		 FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode 55.1 dBFS
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C 54.9
TA = TMIN to TMAX 52.5
TA = 25°C, calibration = BG 54.8
TA = TMIN to TMAX, calibration = BG 52.4
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode 52.5
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode 50
SINAD Signal-to-noise and distortion ratio, integrated across entire Nyquist bandwidth
Input frequency-dependent interleaving spurs included		 FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode 55 dBFS
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C 54.8
TA = TMIN to TMAX 52.3
TA = 25°C, calibration = BG 54.7
TA = TMIN to TMAX, calibration = BG 52.2
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode 52.4
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode 50
ENOB Effective number of bits, integrated across entire Nyquist bandwidth
Input frequency-dependent interleaving spurs included		 FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode 8.8 Bits
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C 8.8
TA = TMIN to TMAX 8.4
TA = 25°C, calibration = BG 8.8
TA = TMIN to TMAX, calibration = BG 8.4
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode 8.4
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode 8
SFDR Spurious-free dynamic range
Input frequency-dependent interleaving spurs included		 FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode 66.7 dBFS
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C 71.6
TA = TMIN to TMAX 61
TA = 25°C, calibration = BG 70
TA = TMIN to TMAX, calibration = BG 59
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode 65.2
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode 58.6
ƒS/2 Interleaving offset spur at ½ sampling rate FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C –77 dBFS
TA = TMIN to TMAX –59.5
TA = 25°C, calibration = BG –74
TA = TMIN to TMAX, calibration = BG –57.5
ƒS/4 Interleaving offset spur at ¼ sampling rate FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C –70 dBFS
TA = TMIN to TMAX –54.5
TA = 25°C, calibration = BG –68
TA = TMIN to TMAX, calibration = BG –53
ƒS/2 – FIN Interleaving offset spur at ½ sampling rate – input frequency FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C –78 dBFS
TA = TMIN to TMAX –62
TA = 25°C, calibration = BG –76
TA = TMIN to TMAX, calibration = BG –61
ƒS/4 + FIN Interleaving offset spur at ¼ sampling rate + input frequency FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C –76 dBFS
TA = TMIN to TMAX –61
TA = 25°C, calibration = BG –71
TA = TMIN to TMAX, calibration = BG –59
ƒS/4 – FIN Interleaving offset spur at ¼ sampling rate – input frequency FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C –77 dBFS
TA = TMIN to TMAX –61.4
TA = 25°C, calibration = BG –76
TA = TMIN to TMAX, calibration = BG –61
THD Total harmonic distortion FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode –73 dBFS
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C –70
TA = TMIN to TMAX –61
TA = 25°C, calibration = BG –72
TA = TMIN to TMAX, calibration = BG –62
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode –68
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode –68
HD2 Second harmonic distortion FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode –72 dBFS
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C –79
TA = TMIN to TMAX –62
TA = 25°C, calibration = BG –81
TA = TMIN to TMAX, calibration = BG –64
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode –76
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode –70
HD3 Third harmonic distortion FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode –72 dBFS
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C –75
TA = TMIN to TMAX –63
TA = 25°C, calibration = BG –81
TA = TMIN to TMAX, calibration = BG –64
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode –70
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode –76
NSD Noise spectral density, average NSD across Nyquist bandwidth 12-bit DDC bypass mode, ADC12J2700, ƒ(DEVCLK) = 2.7 GHz 50-Ω AC-coupled terminated input –147.3 dBFS/Hz
–149.1 dBm/Hz
FIN = 600 MHz, –1 dBFS –146.2 dBFS/Hz
–148.0 dBm/Hz
DDC BYPASS MODE, ADC12J1600, ƒ(DEVCLK) = 1.6 GHz
SNR Signal-to-noise ratio, integrated across entire Nyquist bandwidth
Input frequency-dependent interleaving spurs included		 FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode 55.3 dBFS
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C 54.9
TA = TMIN to TMAX 52.3
TA = 25°C, calibration = BG 54.8
TA = TMIN to TMAX, calibration = BG 52.2
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode 52.5
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode 49.8
SINAD Signal-to-noise and distortion ratio, integrated across entire Nyquist bandwidth
Input frequency-dependent interleaving spurs included		 FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode 55.2 dBFS
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C 54.8
TA = TMIN to TMAX 52.1
TA = 25°C, calibration = BG 54.7
TA = TMIN to TMAX, calibration = BG 52
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode 52.4
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode 49.7
ENOB Effective number of bits, integrated across entire Nyquist bandwidth
Input frequency-dependent interleaving spurs included		 FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode 8.9 Bits
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C 8.8
TA = TMIN to TMAX 8.4
TA = 25°C, calibration = BG 8.8
TA = TMIN to TMAX, calibration = BG 8.4
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode 8.4
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode 8
SFDR Spurious-free dynamic range
Input frequency-dependent interleaving spurs included		 FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode 72.9 dBFS
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C 74.8
TA = TMIN to TMAX 61.8
TA = 25°C, calibration = BG 71
TA = TMIN to TMAX, calibration = BG 60.7
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode 66.7
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode 59.8
ƒS/2 Interleaving offset spur at ½ sampling rate FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C –77 dBFS
TA = TMIN to TMAX –59.8
TA = 25°C, calibration = BG –73
TA = TMIN to TMAX, calibration = BG –57.3
ƒS/4 Interleaving offset spur at ¼ sampling rate FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C –72 dBFS
TA = TMIN to TMAX –54.3
TA = 25°C, calibration = BG –69
TA = TMIN to TMAX, calibration = BG –54
ƒS/2 – FIN Interleaving offset spur at ½ sampling rate – input frequency FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C –77 dBFS
TA = TMIN to TMAX –62
TA = 25°C, calibration = BG –79
TA = TMIN to TMAX, calibration = BG –62
ƒS/4 + FIN Interleaving offset spur at ¼ sampling rate + input frequency FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C –76 dBFS
TA = TMIN to TMAX –61.8
TA = 25°C, calibration = BG –74
TA = TMIN to TMAX, calibration = BG –61
ƒS/4 – FIN Interleaving offset spur at ¼ sampling rate – input frequency FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C –76 dBFS
TA = TMIN to TMAX –62
TA = 25°C, calibration = BG –77
TA = TMIN to TMAX, calibration = BG –61
THD Total harmonic distortion FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode –72 dBFS
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C –72
TA = TMIN to TMAX –60.9
TA = 25°C, calibration = BG –71
TA = TMIN to TMAX, calibration = BG –61
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode –69
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode –69
HD2 Second harmonic distortion FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode –79 dBFS
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C –78
TA = TMIN to TMAX –62
TA = 25°C, calibration = BG –79
TA = TMIN to TMAX, calibration = BG –63
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode –73
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode –70
HD3 Third harmonic distortion FIN = 350 MHz, –1 dBFS, 12-bit DDC bypass mode –76 dBFS
FIN = 600 MHz, –1 dBFS, 12-bit DDC bypass mode TA = 25°C –81
TA = TMIN to TMAX –65
TA = 25°C, calibration = BG –76
TA = TMIN to TMAX, calibration = BG –61
FIN = 1500 MHz, –1 dBFS, 12-bit DDC bypass mode –72
FIN = 2400 MHz, –1 dBFS, 12-bit DDC bypass mode –76
NSD Noise spectral density, average NSD across Nyquist bandwidth 12-bit DDC bypass mode, ADC12J1600, ƒ(DEVCLK) = 1.6 GHz 50-Ω AC-coupled terminated input –145 dBFS/Hz
–146.8 dBm/Hz
FIN = 600 MHz, –1 dBFS –143.9 dBFS/Hz
–145.7 dBm/Hz
DECIMATE-BY-8 MODE, ADC12J2700, ƒ(DEVCLK) = 2.7 GHz
SNR Signal-to-noise ratio, integrated across DDC output bandwidth
Interleaving spurs included		 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode 62.8 dBFS
Calibration = BG 62.7
FIN = 2400 MHz, –1 dBFS, Decimate-by-8 mode 53.3
SINAD Signal-to-noise and distortion ratio, integrated across DDC output bandwidth
Interleaving spurs included		 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode 62.8 dBFS
Calibration = BG 62.7
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode 53.3
ENOB Effective number of bits, integrated across DDC output bandwidth
Interleaving spurs included		 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode 10.1 Bits
Calibration = BG 10.1
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode 8.6
SFDR Spurious-free dynamic range
Interleaving spurs included		 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode 75.9 dBFS
Calibration = BG 74.7
ƒS/2 Interleaving offset spur at ½ sampling rate(4) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –73 dBFS
Calibration = BG –72
ƒS/4 Interleaving offset spur at ¼ sampling rate(4) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –70 dBFS
Calibration = BG –70
ƒS/2 – FIN Interleaving spur at ½ sampling rate – input frequency(4) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –80 dBFS
Calibration = BG –79
ƒS/4 + FIN Interleaving spur at ¼ sampling rate + input frequency(4) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –73 dBFS
Calibration = BG –70
ƒS/4 – FIN Interleaving spur at ¼ sampling rate – input frequency(4) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –77 dBFS
Calibration = BG –77
THD Total harmonic distortion(4) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –70 dBFS
calibration = BG –71
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode –65
HD2 Second harmonic distortion(4) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –78 dBFS
Calibration = BG –76
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode –67
HD3 Third harmonic distortion(4) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –74 dBFS
Calibration = BG –81
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode –73
DECIMATE-BY-8 MODE, ADC12J1600, ƒ(DEVCLK) = 1.6 GHz
SNR Signal-to-noise ratio, integrated across DDC output bandwidth
Interleaving spurs included		 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode 63.5 dBFS
Calibration = BG 63.4
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode 55.8
SINAD Signal-to-noise and distortion ratio, integrated across DDC output bandwidth
Interleaving spurs included		 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode 63.5 dBFS
Calibration = BG 63.4
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode 55.8
ENOB Effective number of bits, integrated across DDC output bandwidth
Interleaving spurs included		 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode 10.3 Bits
Calibration = BG 10.2
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode 9.0
SFDR Spurious-free dynamic range
Interleaving Spurs Included		 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode 76.2 dBFS
Calibration = BG 76.7
ƒS/2 Interleaving offset spur at ½ sampling rate(4) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –73 dBFS
Calibration = BG –72
ƒS/4 Interleaving offset spur at ¼ sampling rate(4) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –70 dBFS
Calibration = BG –69
ƒS/2 – FIN Interleaving spur at ½ sampling rate – input frequency(4) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –78 dBFS
Calibration = BG –79
ƒS/4 + FIN Interleaving spur at ¼ sampling rate + input frequency(4) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –76 dBFS
Calibration = BG –77
ƒS/4 – FIN Interleaving spur at ¼ sampling rate – input frequency(4) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –77 dBFS
Calibration = BG –72
THD Total harmonic distortion(4) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –71 dBFS
Calibration = BG –71
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode –63
HD2 Second harmonic distortion(4) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –77 dBFS
Calibration = BG –78
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode –65
HD3 Third harmonic distortion(4) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –80 dBFS
Calibration = BG –77
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode –74
DDC CHARACTERISTICS
Alias protection(2) 80 dB
Alias protected bandwidth(2) 80 % of output BW
SFDR-DDC Spurious-free dynamic range of digital down-converter(2) 100 dB
Implementation loss(2) 0.5 dB
ANALOG INPUT CHARACTERISTICS
VID(VIN) Full-scale analog-differential input range Minimum FSR setting(5) 500 mVPP
Default FSR setting, TA = TMIN to TMAX 650 725 800
Maximum FSR setting(5) 950
CI(VIN) Analog input capacitance(2) Differential 0.05 pF
Each input pin to ground 1.5 pF
RID(VIN) Differential input resistance 80 95 110 Ω
FPBW Full power bandwidth –3 dB — calibration = BG 2.8 GHz
–3 dB — calibration = FG 3.2
Gain flatness DC to 2 GHz 1.2 dB
2 GHz to 4 GHz 3.8
DC to 2 GHz — calibration = BG 1.5
2 GHz to 4 GHz — calibration = BG 4.5
ANALOG OUTPUT CHARACTERISTICS (VCMO, VBG)
V(VCMO) Common-mode output voltage I(VCMO) = ±100 µA, TA = 25°C 1.225 V
I(VCMO) = ±100 µA, TA = TMIN to TMAX 1.185 1.265
TCVO(VCMO) Common-mode output-voltage temperature coefficient TA = TMIN to TMAX -21 ppm/°C
C(LOAD_VCMO) Maximum VCMO output load capacitance 80 pF
VO(BG) Bandgap reference output voltage I(BG) = ±100 µA, TA = 25°C 1.248 V
I(BG) = ±100 µA, TA = TMIN to TMAX 1.195 1.3
TCVref(BG) Bandgap reference voltage temperature coefficient TA = TMIN to TMAX,
I(BG) = ±100 µA		 0 ppm/°C
C(LOAD_BG) Maximum bandgap reference output load capacitance 80 pF
TEMPERATURE DIODE CHARACTERISTICS
V(TDIODE) Temperature diode voltage slope Offset voltage (approx. 0.77 V) varies with process and must be measured for each part. Offset measurement should be done with PowerDown=1 to minimize device self-heating. 100-µA forward current
Device active		 –1.6 mV/°C
100-µA forward current
Device in power-down		 –1.6 mV/°C
CLOCK INPUT CHARACTERISTICS (DEVCLK±, SYSREF±, SYNC~/TMST±)
VID(CLK) Differential clock input level Sine wave clock, TA = TMIN to TMAX 0.4 0.6 2 VPP
Square wave clock, TA = TMIN to TMAX 0.4 0.6 2 VPP
II(CLK) Input current VI = 0 or VI = VA ±1 µA
CI(CLK) Input capacitance(2) Differential 0.02 pF
Each input to ground 1 pF
RID(CLK) Differential input resistance TA = 25°C 95 Ω
TA = TMIN to TMAX 80 110 Ω
CML OUTPUT CHARACTERISTICS (DS0–DS7±)
VOD Differential output voltage Assumes ideal 100-Ω load
Measured differentially
Default pre-emphasis setting		 280 305 330 mV peak
VO(ofs) Output offset voltage 0.6 V
IOS Output short-circuit current Output+ and output– shorted together ±6 mA
Output+ or output– shorted to 0 V 12
ZOD Differential output impedance 100 Ω
LVCMOS INPUT CHARACTERISTICS (SDI, SCLK, SCS, SYNC~)
VIH Logic high input voltage See (5) 0.83 V
VIL Logic low input voltage See (5) 0.4 V
CI Input capacitance(2)(6) Each input to ground 1 pF
LVCMOS OUTPUT CHARACTERISTICS (SDO, OR_T0, OR_T1)
VOH CMOS H level output IOH = –400 µA(5) 1.65 1.9 V
VOL CMOS L level output IOH = 400 µA(5) 0.01 0.15 V
POWER SUPPLY CHARACTERISTICS
ADC12J2700, ƒ(DEVCLK) = 2.7 GHz
I(VA19) Analog 1.9-V supply current PD = 0, calibration = FG, bypass DDC 457 495 mA
PD = 0, calibration = BG, bypass DDC 557 594
PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 557 598
I(VA12) Analog 1.2-V supply current PD = 0, calibration = FG, bypass DDC 245 296 mA
PD = 0, calibration = BG, bypass DDC 261 312
PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 270 322
I(VD12) Digital 1.2-V supply current PD = 0, calibration = FG, bypass DDC 330 541 mA
PD = 0, calibration = BG, bypass DDC 341 588
PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 366 610
PC Power consumption PD = 0, calibration = FG, bypass DDC 1.56 1.94 W
PD = 0, calibration = BG, bypass DDC 1.78 2.21
PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 1.82 2.25
PD = 1 < 50 mW
ADC12J1600, ƒ(DEVCLK) = 1.6 GHz
I(VA19) Analog 1.9-V supply current PD = 0, calibration = FG, bypass DDC 454 493 mA
PD = 0, calibration = BG, bypass DDC 553 591
PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 553 598
I(VA12) Analog 1.2-V supply current PD = 0, calibration = FG, bypass DDC 180 222 mA
PD = 0, calibration = BG, bypass DDC 190 233
PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 196 243
I(VD12) Digital 1.2-V supply current PD = 0, calibration = FG, bypass DDC 225 460 mA
PD = 0, calibration = BG, bypass DDC 237 529
PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 255 568
PC Power consumption PD = 0, calibration = FG, bypass DDC 1.35 1.75 W
PD = 0, calibration = BG, bypass DDC 1.56 2.04
PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 1.59 2.11
PD = 1 < 50 mW
(1) To ensure accuracy, the VA19, VA12, and VD12 pins are required to be well bypassed. Each supply pin must be decoupled with one or more bypass capacitors.
(2) This parameter is specified by design and is not tested in production.
(3) Interleave related fixed frequency spurs at ƒS / 4 and ƒS / 2 are excluded from all SNR, SINAD, ENOB and SFDR specifications. The magnitude of these spurs is provided separately.
(4) Magnitude of reported tones in output spectrum of ADC core. This tone will only be present in the DDC output for specific Decimation and NCO settings. Careful frequency planning can be used to intentionally place unwanted tones outside the DDC output spectrum.
(5) This parameter is specified by design, characterization, or both and is not tested in production.
(6) The digital control pin capacitances are die capacitances only and is in addition to package and bond-wire capacitance of approximately 0.4 pF.