SNAS411P August 2008 – April 2017 ADC128S102QML-SP
请参考 PDF 数据表获取器件具体的封装图。
There are three major power supply concerns with this product: power supply sequencing, power management, and the effect of digital supply noise on the analog supply.
The ADC128S102 is a dual-supply device. The two supply pins share ESD resources, so care must be exercised to ensure that the power is applied in the correct sequence. To avoid turning on the ESD diodes, the digital supply (VD) cannot exceed the analog supply (VA) by more than 300 mV, during a conversion cycle. Therefore, VA must ramp up before or concurrently with VD.
The ADC128S102 is fully powered-up whenever CS is low and fully powered-down whenever CS is high, with one exception. If operating in continuous conversion mode, the ADC128S102 automatically enters power-down mode between SCLK's 16th falling edge of a conversion and SCLK's 1st falling edge of the subsequent conversion (see Figure 1).
In continuous conversion mode, the ADC128S102 can perform multiple conversions back to back. Each conversion requires 16 SCLK cycles and the ADC128S102 will perform conversions continuously as long as CS is held low. Continuous mode offers maximum throughput.
In burst mode, the user may trade off throughput for power consumption by performing fewer conversions per unit time. This means spending more time in power-down mode and less time in normal mode. By utilizing this technique, the user can achieve very low sample rates while still utilizing an SCLK frequency within the electrical specifications. The Power Consumption versus SCLK curve in the Typical Characteristics shows the typical power consumption of the ADC128S102. To calculate the power consumption (PC), simply multiply the fraction of time spent in the normal mode (tN) by the normal mode power consumption (PN), and add the fraction of time spent in shutdown mode (tS) multiplied by the shutdown mode power consumption (PS) as shown in Equation 1.
The charging of any output load capacitance requires current from the digital supply, VD. The current pulses required from the supply to charge the output capacitance will cause voltage variations on the digital supply. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, if the analog and digital supplies are tied directly together, the noise on the digital supply will be coupled directly into the analog supply, causing greater performance degradation than would noise on the digital supply alone. Similarly, discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise in the substrate that will degrade noise performance if that current is large enough. The larger the output capacitance, the more current flows through the die substrate and the greater the noise coupled into the analog channel.
The first solution to keeping digital noise out of the analog supply is to decouple the analog and digital supplies from each other or use separate supplies for them. To keep noise out of the digital supply, keep the output load capacitance as small as practical. If the load capacitance is greater than 50 pF, use a 100-Ω series resistor at the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge current of the output capacitance and improve noise performance. Because the series resistor and the load capacitance form a low frequency pole, verify signal integrity once the series resistor has been added.