SNAS411P August   2008  – April 2017 ADC128S102QML-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: ADC128S102QML-SP Converter
    6. 6.6 Electrical Characteristics: Radiation
    7. 6.7 Electrical Characteristics: Burn in Delta Parameters - TA at 25°C
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 ADC128S102 Transfer Function
      2. 7.3.2 Analog Inputs
      3. 7.3.3 Digital Inputs and Outputs
      4. 7.3.4 Radiation Environments
        1. 7.3.4.1 Total Ionizing Dose
        2. 7.3.4.2 Single Event Latch-Up and Functional Interrupt
        3. 7.3.4.3 Single Event Upset
    4. 7.4 Device Functional Modes
      1. 7.4.1 ADC128S102 Operation
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Sequence
    2. 9.2 Power Management
    3. 9.3 Power Supply Noise Considerations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Specification Definitions
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Engineering Samples

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • NAC|16
  • Y|0
  • NAD|16
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

NAC Package
16-Pin CFP
Top View

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
ANALOG I/O
IN0 to IN7 4 Input (Analog) Analog inputs. These signals can range from 0 V to VREF.
5
6
7
8
9
10
11
DIGITAL I/O
CS 1 Input (Digital) Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long as CS is held low.
DIN 14 Input (Digital) Digital data input. The ADC128S102QML-SP's Control Register is loaded through this pin on rising edges of the SCLK pin.
DOUT 15 Output (Digital) Digital data output. The output samples are clocked out of this pin on the falling edges of the SCLK pin.
SCLK 16 Input (Digital) Digital clock input. The specified performance range of frequencies for this input is 0.8 MHz to 16 MHz. This clock directly controls the conversion and readout processes.
POWER SUPPLY
AGND 3 Ground The ground return for the analog supply and signals.
DGND 12 Ground The ground return for the digital supply and signals.
VA 2 Supply Positive analog supply pin. This voltage is also used as the reference voltage. This pin should be connected to a quiet 2.7 V to 5.25 V source and bypassed to GND with 1-µF and 0.1-µF monolithic ceramic capacitors located within 1 cm of the power pin.
VD 13 Supply Positive digital supply pin. This pin should be connected to a 2.7 V to VA supply, and bypassed to GND with a 0.1-µF monolithic ceramic capacitor located within 1 cm of the power pin.