SNAS747 June   2017 ADC081S101-MIL

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  7. 7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Determining Throughput
    4. 8.4 Device Functional Modes
      1. 8.4.1 ADC081S101-MIL Transfer Function
      2. 8.4.2 Modes Of Operation
        1. 8.4.2.1 Normal Mode
        2. 8.4.2.2 Shutdown Mode
  9. 9 Applications Information
    1. 9.1 Analog Input
      1. 9.1.1 Digital Inputs And Outputs
    2. 9.2 Typical Application Circuit
  10. 10Power Supply Recommendations
    1. 10.1 Noise Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(3)(2)
MIN MAX UNIT
Analog supply voltage, VA –0.3 6.5 V
Voltage on any analog pin to GND –0.3 VA + 0.3 V
Input current at any pin(4) ±10 mA
Package input current(4) ±20 mA
Power consumption at TA = 25°C See(5)
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the TI Office/Distributors for availability and specifications.
(3) All voltages are measured with respect to GND = 0 V, unless otherwise specified.
(4) When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin must be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. These specifications do not apply to the VA pin. The current into the VA pin is limited by the analog supply voltage specification.
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation listed above is reached only when the device is operated in a severe fault condition (that is, when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions must always be avoided.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge(1) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(2) ±3500 V
Machine model (MM) ±300
(1) Human body model is 100-pF capacitor discharged through a 1.5-kΩ resistor. Machine model is 220 pF discharged through 0 Ω.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VA Supply voltage 2.7 5.25 V
Digital input pins voltage (regardless of supply voltage) –0.3 5.25 V
Analog input pins voltage 0 VA V
Clock frequency 25 20000 kHz
Sample rate 1 Msps
TA Operating temperature –40 85 °C
(1) All voltages are measured with respect to GND = 0 V, unless otherwise specified.

6.4 Thermal Information

THERMAL METRIC(1) ADC081S021 UNIT
DBV (SOT-23) NGF (WSON)
6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 184.5 99.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 151.2 118.3 °C/W
RθJB Junction-to-board thermal resistance 29.7 68.9 °C/W
ψJT Junction-to-top characterization parameter 29.8 6.6 °C/W
ψJB Junction-to-board characterization parameter 29.1 69.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — 14.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

The following specifications apply for VA = 2.7 V to 5.25 V, GND = 0V, fSCLK = 10 MHz to 20 MHz, CL = 15 pF fSAMPLE = 500 ksps to 1 Msps, and TA = 25°C, unless otherwise noted. (1)
PARAMETER TEST CONDITIONS MIN(2) TYP MAX(2) UNIT
STATIC CONVERTER CHARACTERISTICS
Resolution with no missing codes 8 Bits
INL Integral non-linearity TA = 25°C ±0.05 LSB
TA = TMINto TMAX ±0.3
DNL Differential non-linearity TA = 25°C ±0.07 LSB
TA = TMINto TMAX ±0.3
VOFF Offset error TA = 25°C ±0.03 LSB
TA = TMINto TMAX ±0.3
GE Gain error TA = 25°C ±0.08 LSB
TA = TMINto TMAX ±0.4 LSB
TUE Total unadjusted error TA = 25°C ±0.07 LSB
TA = TMINto TMAX ±0.3
DYNAMIC CONVERTER CHARACTERISTICS
SINAD Signal-to-noise
plus distortion ratio		 VA = 2.7 V to 5.25 V, fIN = 100 kHz,
–0.02 dBFS		 49.7 dB
TA = TMINto TMAX 49
SNR Signal-to-noise ratio VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS 49.7 dB
THD Total harmonic distortion VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS –77 dB
TA = TMINto TMAX –65
SFDR Spurious-free dynamic range VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS 68 dB
TA = TMINto TMAX 65
ENOB Effective number of bits VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS 7.9 Bits
TA = TMINto TMAX 7.8
IMD Intermodulation distortion,
second order terms		 VA = 5.25 V, fa = 103.5 kHz, fb = 113.5 kHz –68 dB
Intermodulation distortion,
third order terms		 VA = 5.25 V, fa = 103.5 kHz, fb = 113.5 kHz –68 dB
FPBW –3 dB full power bandwidth VA = 5 V 11 MHz
VA = 3 V 8 MHz
ANALOG INPUT CHARACTERISTICS
VIN Input range 0 to VA V
IDCL DC leakage current TA = TMINto TMAX ±1 µA
CINA Input capacitance Track mode 30 pF
Hold mode 4 pF
DIGITAL INPUT CHARACTERISTICS
VIH Input high voltage VA = 5.25 V, TA = TMINto TMAX 2.4 V
VA = 3.6 V, TA = TMINto TMAX 2.1 V
VIL Input low voltage VA = 5 V, TA = TMINto TMAX 0.8 V
VA = 3 V, TA = TMINto TMAX 0.4 V
IIN Input current VIN = 0 V or VA ±10 nA
VIN = 0 V or VA, TA = TMINto TMAX ±1 µA
CIND Digital input capacitance 2 pF
TA = TMINto TMAX 4
DIGITAL OUTPUT CHARACTERISTICS
VOH Output high voltage ISOURCE = 200 µA VA – 0.07 V
ISOURCE = 200 µA, TA = TMINto TMAX VA – 0.2
ISOURCE = 1 mA VA – 0.1 V
VOL Output low voltage ISINK = 200 µA 0.03 V
ISINK = 200 µA, TA = TMINto TMAX 0.4
ISINK = 1 mA 0.1 V
IOZH, IOZL TRI-STATE leakage current ±0.1 µA
TA = TMINto TMAX ±10
COUT TRI-STATE output capacitance 2 pF
TA = TMINto TMAX 4
Output coding Straight (natural) binary
POWER SUPPLY CHARACTERISTICS
VA Supply voltage TA = TMINto TMAX 2.7 5.25 V
IA Supply current, normal mode
(operational, CS low)		 VA = 5.25 V, fSAMPLE = 1 k\Msps, SOT-23 and WSON 2.0 mA
VA = 5.25 V, fSAMPLE = 1 k\Msps, TA = TMINto TMAX, SOT-23 3.2
VA = 5.25 V, fSAMPLE = 1 k\Msps, TA = TMINto TMAX, WSON 2.6
VA = 3.6 V, fSAMPLE = 1 Msps, SOT-23 and WSON 0.6 mA
VA = 3.6 V, fSAMPLE = 1 Msps, TA = TMINto TMAX, SOT-23 1.5
VA = 3.6 V, fSAMPLE = 1 Msps, TA = TMINto TMAX, WSON 1.1
Supply current, shutdown
(CS high)		 fSCLK = 0 MHz, VA = 5.25 V, fSAMPLE = 0 ksps 500 nA
fSCLK = 20 MHz, VA = 5.25 V, fSAMPLE = 0 ksps 60 µA
PD Power consumption, normal mode
(operational, CS low)		 VA = 5 V, SOT-23 and WSON 10 mW
TA = TMINto TMAX, VA = 5 V, SOT-23 16
TA = TMINto TMAXVA = 5 V, WSON 13
VA = 3 V, SOT-23 and WSON 2.0 mW
TA = TMINto TMAX, VA = 3 V, SOT-23 4.5
TA = TMINto TMAXVA = 3 V, WSON 3.3
Power consumption, shutdown
(CS high)		 fSCLK = 0 MHz, VA = 5 V, fSAMPLE = 0 ksps 2.5 µW
fSCLK = 20 MHz, VA = 5 V, fSAMPLE = 0 ksps 300 µW
AC ELECTRICAL CHARACTERISTICS
fSCLK Clock frequency TA = TMINto TMAX, See(3) 10 20 MHz
fS Sample rate See(3) 50 ksps
TA = TMINto TMAX, See(3) 500
TA = TMINto TMAX 1 Msps
tHOLD Hold time, falling edges TA = TMINto TMAX 13 SCLK
DC SCLK duty cycle fSCLK = 20 MHz 50%
TA = TMINto TMAX, fSCLK = 20 MHz 40% 60%
tACQ Minimum time required for acquisition TA = TMINto TMAX 350 ns
tQUIET Quiet time TA = TMINto TMAX, See(4) 50 ns
tAD Aperture delay 3 ns
tAJ Aperture jitter 30 ps
(1) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).
(2) Data sheet minimum and maximum specification limits are specified by design, test, or statistical analysis.
(3) This is the frequency range over which the electrical performance is ensured. The device is functional over a wider range which is specified under Operating Ratings.
(4) Minimum quiet time required by bus relinquish and the start of the next conversion.

6.6 Timing Requirements

The following specifications apply for VA = 2.7 V to 5.25 V, GND = 0 V, fSCLK = 10.0 MHz to 20.0 MHz, CL = 25 pF, fSAMPLE = 500 ksps to 1 Msps, and TA = 25°C (unless otherwise noted).(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tCS Minimum CS pulse width TA = TMINto TMAX 10 ns
tSU CS to SCLK setup time TA = TMINto TMAX 10 ns
tEN Delay from CS until SDATA TRI-STATE disabled(2) TA = TMINto TMAX 20 ns
tACC Data access time after SCLK falling edge(3) VA = 2.7 V to 3.6 V,
TA = TMINto TMAX		 40 ns
VA = 4.75 V to 5.25 V,
TA = TMINto TMAX		 20 ns
tCL SCLK low pulse width TA = TMINto TMAX 0.4 × tSCLK ns
tCH SCLK high pulse width TA = TMINto TMAX 0.4 × tSCLK ns
tH SCLK to data valid hold time VA = 2.7 V to 3.6 V,
TA = TMINto TMAX		 7 ns
VA = 4.75 V to 5.25 V,
TA = TMINto TMAX		 5 ns
tDIS SCLK falling edge to SDATA high impedance(4) VA = 2.7 V to 3.6 V,
TA = TMINto TMAX		 6 25 ns
VA = 4.75 V to 5.25 V,
TA = TMINto TMAX		 5 25 ns
tPOWER-UP Power-up time from full power down TA = 25°C 1 µs
(1) Data sheet minimum and maximum specification limits are specified by design, test, or statistical analysis.
(2) Measured with the timing test circuit and defined as the time taken by the output signal to cross 1 V.
(3) Measured with the timing test circuit and defined as the time taken by the output signal to cross 1 V or 2 V.
(4) tDIS is derived from the time taken by the outputs to change by 0.5 V with the timing test circuit. The measured number is then adjusted to remove the effects of charging or discharging the output capacitance. This means that tDIS is the true bus relinquish time, independent of the bus loading.
ADC081S101-MIL 20145708.gif Figure 1. Timing Test Circuit
ADC081S101-MIL 20145706.gif Figure 2. ADC081S101-MIL Serial Timing Diagram