Quality, reliability & packaging FAQs

Established in 1985, this comprehensive system has been integral to TI’s ability to deliver leadership analog and embedded processing products from its worldwide manufacturing base.

Please refer to the Quality System Manual (QSM000) for our Quality Management System policies and procedures.

TI’s quality guidelines outline measures to ensure compliance of our components with a variety of quality specifications. These guidelines apply to how TI handles materials, manufacturing processes, tests, controls, handling, storage, transport and delivery of TI products to its customers. 

Please see our general quality guidelines for more information.

TI complies with the requirement in JESD46, latest issue for notification of product changes. Consistent with this industry standard, customers will be notified of major changes which affect the form, fit, function, or adversely affect quality or reliability of the product. For custom devices, Texas Instruments will not implement a change until customer approval is received. 

For more information, please visit our product change notification page.

TI makes an effort to not obsolete products out of convenience. Convenience means a low running device, poor yields, limited customer adoption or similar items. TI’s obsolescence withdrawal schedule provides a longer lead time than the industry standard. TI allows 12 months for the last order and an additional six months to take final delivery of obsolete items. 

In rare circumstances, an accelerated withdrawal schedule may be necessary. In such cases, TI will communicate the last buy and final delivery dates in the end of life (EOL) notice, along with an explanation of the circumstances necessitating the early withdrawal.

Quality and reliability are built into TI’s culture, with the goal of providing customers high quality products. TI’s semiconductor technologies are developed with a minimum goal of fewer than 50 Failures in Time (FIT) at 100,000 Power-On-Hours at 105C junction temperature. TI builds simulations, accelerated testing, and robustness evaluations into the product development process. During the product development process, TI carefully assesses silicon process reliability, package reliability, and silicon/package interaction.

Non-Automotive devices are qualified with industry standard test methodologies performed primarily to the intent of the Joint Electron Devices Engineering Council (JEDEC). TI qualifies new devices, significant changes, and product families based on JEDEC standard JESD47. TI evaluates manufacturability of devices to verify a robust silicon and assembly flow to enable continuity of supply to customer.

Automotive devices are qualified with industry standard test methodologies performed primarily to the intent of the Automotive Electronics Council (AEC) Q100 standard.  AEC Q100 is an automotive industry standard that specifies the recommended new product and major change qualification requirements and procedures.   See the Automotive Qualification section below for additional information about parts meeting the AEC-Q100 standard. 

The Q100 product is qualified based on the temperature grade. The stressing for Q100 product is pre and post tested at room and hot temperature per the grade pre and post reliability stress. The commercial product is only tested at room temperature post reliability stress. 

Grade 0 (-40 to 150°C), Grade 1(-40 to 125°C), Grade 2 (-40 to 105°C), and Grade 3 (-40 to 85°C) have different stress conditions. Depending on where the product is used in the automotive application will generally dictate the grade. For example, if the application is under the hood, Grade 0 will be used to withstand very high temperature environment. The qualification requirements are more stringent based on the grade of the device.

Qualification Summaries for TI Products can be found on TI.com.  Please see the TI Qualification Summary Tool for further information.

HTOL is performed to determine the reliability of devices under operation at high temperature conditions over an extended period of time.  The parts are subjected to a specified electrical bias for a specified amount of time temperature. 

The rating provides attenuation to prevent damage to the device during an ESD transient (2KV) during normal handling during manufacturing where IC’s are handled.

Components may be assembled on a printed wiring board (PWB) for stress testing.

This stress is done to assess the ability of a device to withstand the thermal stress of the soldering process by simulating board mounting. The soak condition is determined by JEDEC which specifies performing Moisture Reflow Sensitivity Classification per IPC/JEDEC J-STD-020. 

The AEC Council has guidelines on the use of the tools and methods to use to reduce defects with the ultimate goal of zero defects. Some examples are DFMEA (Design Failure Modes and Effects Analysis), PFMEA (Process Failure Modes and Effects Analysis), and SPC (Statistical Process Control). TI incorporates these defect reduction systems in our design and manufacturing processes.  

It is a global Quality Management System Standard for the Automotive industry. Texas Instruments manufacturing sites are certified to IATF 16949. View TI certifications here.

AEC-Q006 is the Automotive Electronics Council qualification standard that specifies requirements for components using copper (Cu) wire interconnections in automotive products.

TI devices are qualified to the current version of AEC-Q100 at the time the device was released. AEC documents can be found at   http://www.aecouncil.com/

Products are tested at multiple voltages levels for HBM and CDM. Individual device sensitivities such as feature sizes and die size may affect passing voltage level.  The HBM classification table is in ANSI/ESDA/JEDEC JS-001-2017 and CDM levels per JESD22-C101 in JEDEC.

TI follows the JEDEC ESD standards for testing. The TI part may have been tested to the same voltage as the competitor, but the TI datasheet specified a lower voltage for margin. This assures the part meets that level over time. The Industry standard minimum component levels for HBM (1KV) and CDM (250V) are considered a safe target for manufacturing and handling of today’s products using basic ESD control methods.

Please refer to following ESD council articles on safe ESD levels.

A Case for Lowering Component Level CDM ESD Specifications and Requirements

Per JEDEC, either Autoclave or unbiased HAST may be run. Autoclave is not recommended for Ball Grid Array (BGA) and Wafer Chip Scale (WCSP) devices. Either HAST (Highly Accelerated Stress Test) or THB stress may be run per JEDEC. THB is recommended for BGA with substrates. HAST may be used to accelerate the THB condition.

Customer product shelf life refers to the amount of time that a customer can properly store a TI product at their site without physical degradation that might subsequently impact manufacturing integrity.

TI stores all products in humidity- and temperature-controlled environments, with appropriate moisture barrier bags and desiccant based on TI internal specifications for moisture sensitivity that align with Joint Electron Device Engineering Council (JEDEC) J-STD-033C: Handling, Packaging, Shipping and Use of Moisture, Reflow and Process Sensitive Devices. TI evaluated the potential risk of long-term storage in the application report, “Component Reliability After Long Term Storage” and the risk assessment published in JEDEC JEP160, “Long-Term Storage for Electronic Solid-State Wafers, Dice and Devices.”

Generally, yes, so long as you have properly stored and handled the products. The exact customer product shelf life for a specific semiconductor product depends on a number of factors, including the type of materials used in the device, manufacturing conditions, moisture sensitivity levels, the use of moisture barrier bags in product packaging, the amount of desiccant used and your storage conditions. As such, the decision to use the products is one that only you can make with these details in mind.

The TI application report, “Component Reliability After Long Term Storage,” describes the risk factors associated with the extended storage of plastic-encapsulated integrated circuits in a warehouse (an uncontrolled indoor environment) and the materials and practices required to assure the quality and reliability of the devices to the customer.

Careful control of our internal manufacturing and logistics processes enables us to deliver products with appropriate product shelf life performance and manage inventory in a way that helps increase supply assurance for our customers. TI’s product shelf life approach benefits TI customers in multiple ways:

• Improved assurance of supply.
• Improved product availability, with reduced lead times.
• Improved handling of end-of-life commitments.
• Assurance of genuine TI-sourced parts.
  
• Assurance that TI has stored the product in a controlled environment and handled it properly.

Please continue to refer to the moisture sensitivity level information on the bag or box for instructions on length of use. Your usage life remains unchanged.

In general, there is no need to bake properly stored products before using them in the production line. TI also includes humidity indicator cards (HIC) within its moisture barrier bags to ensure the product storage has not been compromised. If the HIC shows pink on >10% level, then the parts in that MBB will need baking before use. TI’s Product Distribution Center takes care to ensure the moisture integrity of all material before shipment. For any material that requires repacking, the seal date on the material will indicate the date on which it was repacked.

At TI, environmental compliance and product stewardship is a responsibility we take seriously. Our commitment goes beyond simply doing what is required by rule or regulation with respect to hazardous substances (what TI calls restricted chemicals and materials or RCMs).

Our objective is to conduct our business in such a way that protects and preserves the environment, health and safety of our employees, our customers, and the communities where we all live and operate.

For more information, please visit the environmental information page.

Please see our lead-free information page.

TI believes that the purchase of minerals from mines located in the Democratic Republic of Congo (DRC) or adjoining countries is an important global concern, and we work diligently with our supply chain to ensure that TI products do not contain minerals derived from conflict sources. TI uses industry practices and guidelines and is actively involved in industry groups to source materials, collect information and improve overall industry practices. 

For more information, please visit TI’s conflict mineral page.

TI has a strong history of environmental stewardship and works to continuously improve environmental performance and efficiency at its sites worldwide.

For further information, please view our environmental responsibility page.

For device-specific materials content, please use our material content search tool.  Searches can be for a single or multiple part numbers.  Results include a summary compliance status table & environmental ratings with links to detailed material content information for each specific TI part number. 

TI addresses product end-of-life and disposal issues both as a component manufacturer and as a producer of consumer devices.

For further information, please visit our sustainability page.

RoHS requirements and status

On January 27, 2003, the European Union passed the "Restriction on Use of Hazardous Substances in Electrical and Electronic Equipment," or "RoHS" legislation 2002/95/EC, which becomes effective July 1, 2006. TI’s latest RoHS statement is found on our Environmental information page. It restricted the following substances at the homogenous (material) level with associated maximum thresholds.

Since then, there have been several updates to the Directive, the major ones being2011/65/EU on 8 June 2011 that recasted exemptions expiring in 2011 to future dates (most in 2016).  Amendment EU 2015/863 released on 4 June 2015 and comes into effect 22 July 2019 that added 4 phthalates to the current list of 6 restricted substances:

Further revisions continue to be released and TI will maintain its documentation and requirements as they are released, including information on exemptions that may be required.

Data flags under the RoHS field can be:

Yes:  fully compliant to EU RoHS, no exemption required

RoHS Exempt:  fully compliant to EU RoHS, with an exemption applied

No:  Not compliant to EU RoHS

RoHS restricted substances – ppm calculation

The ppm calculations are at the homogeneous material level and are worst-case ppm for each RoHS substance. 

PPM = (mass of substance / mass of material) * 1,000,000 * total amount of each RoHS substance contained in the material.

EXAMPLE:  Lead (Pb) in leadframe example:

(mass of Lead: 0.006273 mg / total mass of leadframe: 62.730001 mg) * 1,000,000 = 100 ppm

REACH status

The European Union’s Registration Evaluation, Authorization and restriction of Chemicals (EU REACH) that lists the Substances of Very High Concern (SVHC) as well as substances under restriction, REACH Annex XVII. The REACH SVHC list is usually updated 2 times per year and the REACH Annex XVII list updated as needed.  TI’s latest REACH statement is located on our Environmental information page.

Data flags under the REACH field can be:

Yes:  Fully compliant to EU REACH.

Affected: Only used when a REACH SVHC substance(s) is contained above threshold 0.1% REACH Article threshold.  Any REACH SVHC above the threshold is not restricted from use but if contained above threshold, further information must be available.

No:  Not compliant to EU REACH – a restricted substance(s) under REACH Annex XVII is contained outside of allowed application.

Green status

TI’s full definition of Green is within the TI Low Halogen (Green) Statement found on our Environmental information page.

Data flags under the Green field can be:

Yes:  Fully compliant to TI Green defintion.

No:  Not compliant to TI Green defintion.

IEC 62474 DB status

The IEC 62474 database (IEC 62474 DB) is the worldwide regulatory list of restricted substances, applications and thresholds as they apply to electronic products maintained by the IEC 62474 Validation Team committee. This list was the JIG-101 but was sunset in 2012 and became the IEC 62474 DB at that time.

TI products that are compliant to RoHS requirements are also fully compliant to the substances and thresholds defined in the IEC 62474 Database (was previously the Joint Industry Guide).

Data flags under the IEC 62474 DB field can be:

Yes:  Fully compliant to IEC 62474 DB.

Affected:  Compliant to IEC 62474 DB with the use of REACH SVHC substance(s) when contained above threshold, REACH SVHCs are not restricted from use but if contained above threshold, further information must be available.

No:  Not compliant to IEC 62474 DB.

PPM to Mass Percentage conversion table

Substances are reported in parts per million (PPM) and mass %.  A quick guide for conversion between PPM and mass% is as follows:

1 ppm = 0.0001 %

10 ppm = 0.001 %

100 ppm = 0.01 %

1000 ppm = 0.1 %

10000ppm = 1.0 %

Mass (mg)

Representative device weight (per part) in milligrams.  Detailed information at the material and substance level are also reported in mg.

Restricted chemical test report

Quantitative analysis reports of the homogenous components listed in material content declarations.  This data independently confirms content compliance of key restricted substances.

Recyclable metals - ppm

The WEEE Directive (Waste Electrical and Electronic Equipment) has created interest in recyclable metals. TI reports values at the mass (mg) and ppm level.  For WEEE, ppm calculations are at the component level.  An example for calculating the ppm gold content follows.

Example: ppm= 1,000,000 * total amount of gold in component (mg) / total component weight (mg)

Gold mass = 0.23mg & Component mass = 128mg

1,000,0000 * 0.23 mg gold / 128mg component = 1,797 ppm

TI has been International Organization for Standardization (ISO) certified for Quality Management System (ISO 9001) and Environmental Management System (ISO 14001) since 1996 and has maintained compliance to the ISO requirements since that time. 

TI is also TS 16949 certified. TS 16949 is an international quality system standard specifically formulated for the global automotive industry.

For more please see TI’s certifications information.

Plastic encapsulating materials used in TI semiconductor products meet the requirements of UL 94 flame classification V-0 unless stated otherwise on the product datasheet.

Sony requires its suppliers to renew their Sony Green Partner certification every two years. Each manufacturing site must be certified. 

The Canon green certification can be found here.

PPAP, or Production Part Approval Process is an industry-standard process defined by the Automotive Industry Action Group (AIAG) for submitting product information to customers in the automotive industry and obtaining customer approval to ship products.  TI will provide PPAP documentation to any customer purchasing products “Qualified for Automotive Applications” in the TI product datasheet.  For more information, refer to AIAG PPAP Manual 4th Edition. 

ACTIVE products which are qualified for automotive applications.  TI provides PPAP documents for a single, specific Orderable Part Number.

PPAP are intended for customers who have designed a TI automotive product into their application and who follow the PPAP according to automotive industry requirements.

You may request PPAP documentation here.

You can expect to receive level 1 PPAP documentation within the same day and requests for higher levels in 2-4 weeks, depending on the specific request.

• TI Orderable Part Number
• Customer Part Number (if needed)
• PPAP Level
• Customer IMDS ID (if IMDS declaration is needed)
• TI PCN number, available at the top of the PCN letter you received from TI (if requesting a PCN PPAP)

Only one request may be submitted for each TI part number and Customer Part number combination. However, you can modify your request when it has been processed and is in “Pending Customer Approval” or “Closed” status.

You can do so by clicking the “request changes” from your PPAP overview page.  Please note that once approved, PPAPs are locked and unable to be modified.

You can modify the level of your request when it has been processed and is in “Pending Customer Approval” or “Closed” status.

You can do so by clicking the “request changes” from your PPAP overview page.  Please note that once approved, PPAPs are locked and unable to be modified.

Please submit a request to TI’s Customer Support Center, indicating the PPAP request number you would like to retract approval for.  TI will review your case and determine if it is possible to retract the approval.  Please note that PPAP approval is irrevocable after 7 days or after orders have been received by TI – whichever is earlier.

You can see all your PPAP requests by visiting the PPAP request portal.

You may approve any of the PPAPs requested by you, and any TI employee may approve on your behalf based on verbal or written communication.

TI requires PPAPs delivered via TI.com to be reviewed and approved within 21 days. Change requests also need to be submitted to TI within this period. If your PPAP is not approved within 21 days, it will be system-approved on your behalf.  In addition, placement of orders will constitute approval of the latest PPAP provided prior to order placement.

The PPAP request form is quick and easy – less than 10 inputs are required.  TI encourages users to review the required information prior to starting a PPAP request.

Please Contact TI Customer Support for help resolving this issue.

Please Contact TI Customer Support to request an extension.

Please Contact TI Customer Support for help resolving this issue.

Yes, TI offers a wide range of innovative technologies for the modern automobile. Click here to learn more.

Yes, for more information on TI’s space, aerospace and defense products, click here.

TI’s HiRel portfolio provides products in enhanced plastic (EP) packages and full military-class ceramic (QML) packages with extended operating temperature ranges. We offer an expanding portfolio of QML Class Q and V (Qualified to MIL-PRF-38535), MIL-STD-883 and Class-B compliant product lines with extended temperature and radiation-tolerant operating ranges. For the full portfolio, please see TI aerospace and defense product page.

Yes. TI supports space applications by providing MIL-PRF-38535 QML Class V and Radiation Hardness Assured (RHA) components. Please see our space radiation data page for more information.

Please see TI’s military and HiRel products process flows.

SER is soft error rate. Soft errors affect the data state of memories and sequential elements and are caused by random radiation events that occur naturally in the terrestrial environment.  In contrast to hard errors from defects or reliability wear-out mechanisms, soft errors do not typically damage the circuit itself (hence “soft” moniker) but corrupt the stored data or state of the circuit that is afflicted (in digital circuits this corresponds to a ones data state being erroneously flipped to a zero data state or vice versa).

Once new data is written to the memory location the data error is over-written and the system functions correctly. The failure rate induced by soft errors, or SER, is reported in FIT or FIT/Mbit (when focused on memory). In terms of occurrence rate, SER will be many times higher than the hard failure rate of all other mechanism combined. Soft errors are also referred to as a single-event upset (SEU) which better captures the idea that a single radiation event causes the data corruption.

While there are many potential causes of SER, such as a glitch, noise, electromagnetic interference, the dominant cause of SER in well-designed circuits in a qualified manufacturing process are particle radiations.

In the terrestrial environment, the key radiations of concern are alpha particles emitted by trace impurities in the chip materials themselves (alpha particles cannot travel far and thus any alpha particles that reach the silicon are typically emitted from materials within the chip itself), and the ever-present cosmic-background neutron flux that bathes us at sea-level with ~ 13 n/hr-cm2 and at flight altitudes up to 26,000 n/hr-cm2. 

The alpha particle SER is minimized by the use of ultra-low alpha (ULA) materials but the neutrons, being very penetrating cannot easily be shielded, and thus we have to live with a certain level of SER. Further reduction in SER can only be achieved by the use of processes that reduce the amount of charge collected by radiation events (e.g. silicon on insulator) or more commonly, by the use of redundancy circuits (e.g. error correction in memories).

Product technology affects SER to some level, but much more important is the amount of SRAM and sequential logic in the device. Usually devices with large unprotected memories have the highest SER.

Technologies that use reduced voltages for low-power tend to have higher SER since the data state is defined by the voltage and hence lower voltage means lower signal charge and hence the device becomes more sensitive to charge transients caused by radiation. The use of error correction on memory can greatly reduce SER. The use of ULA materials reduces the alpha particle component of SER.

Little can be done to shield the neutrons causing the remaining SER, and indeed, in avionics applications where the neutron flux is 100-1000s of times more intense than ground-level applications, the SER will be much higher.

No. There is no standard or “acceptable level” for SER. This is because “acceptable” SER depends on the application, how much memory is present, whether or not the memory is protected, where the device is operated (e.g. ground-level, aviation altitudes, etc.)

Because of these many factors in accessing the criticality of a bit failure, no single metric can be used for SER on a given general purpose part like a DSP, MSP, etc. The level of acceptable failure should be determined by the customer based on the product application, the software, and various applications details.

The first step to answering this specific question is that one should have some idea of an upper bound for the soft failure rate to judge if further work is needed.

TI was one of the industry drivers of the JEDEC JESD89A “Measurement and reporting of alpha particle and terrestrial cosmic ray induced soft errors in semiconductor devices” test standard as a basis for doing radiation tests with alpha particles and neutrons.

We generally do not test products but designed test chips containing production SRAM arrays and sequential logic arrays to enable accurate modeling of SER. These are combined into an online SER estimator calculator that can be used to gauge the upper-bound for SER in any TI products made in CMOS technologies (350nm to 20nm). The calculator requires an NDA for external customers.

Please see our white paper, TI's Journey to High Volume Copper Wire Bonding Production, for information on the benefits of copper wire bonding, what wire sizes are available, and the physical/mechanical characteristics of copper wire.

Please see SMT and packaging application notes page for specific package’s surface mounting recommendation.

TI’s WEBENCH® thermal information page provides easy access to the tools and information needed to understand and design thermal systems including design tools, lab analysis recommendations, education, and FAQs.

QFN/SONs are packages with a plastic small outline and no lead, with no lead extending beyond the package body. The contact pads are exposed and flush with the bottom of the package.

• Small footprint (yields savings in PCB real estate)
• Thin package (< 1mm package height)
• Excellent thermal performance (Soldering the exposed thermal paddle to the board provides an excellent path for heat transfer from die to the board)
• Smaller size, form factor, and location of contact pads allows parts to be placed closer to the other components on the board
• Negligible package lead inductance
• Uses standard surface mount equipment and flow for PCB assembly
• There are no lead co-planarity issues with this package

QFN/SON packages are offered in a range of pin count, package sizes, and pitches. Please see TI’s package selection tool for more information.

QFN/SONs are LLP stands for “leadless lead frame package" and was the terminology for National’s QFN/SON technology. TI has integrated LLP into the company’s QFN/SON packages. Please see TI’s package selection tool for more information.

Yes, TI offers dual row QFN. You can view the options in our package selection tool, under VQFN-MR and WQFN-MR packaging.

QFN SMT recommendations can be found here. Application notes on QFN/SON and multi-row QFN also include more details.

General guidelines for QFN/SON are included in TI’s Quad Flat Pack No-Lead Logic Packages application note. Based on TI’s experience, these recommended guidelines are important for the end user to follow during PCB design, stencil design and SMT assembly steps to ensure a successful SMT process.

Please click here then enter TI part number into search tool for more information.

Yes, TI lead finishes for QFN/SON will work for both lead free and leaded paste. Please refer to solder manufacturer’s recommended reflow profile for more information.

Please refer to the device’s specific product folder for MSL rating and peak reflow temperature. Within the product folder, the information is located in the ordering & quality section. For example, search for a specific TI.com product, and on the device page click “Ordering & quality”.

Application note AN-1187 has been converted and is now called Leadless Leadframe Package (LLP).

WCSP is packaging technology that includes the following features:

• Package size is equal to die size
• Smallest footprint per I/O count
• Interconnect layout available in 0.3, 0.34, 0.4, and 0.5mm pitch

Two types of PCB land patterns are used for surface mount packages:

• Non-solder mask defined (NSMD)
• Solder mask defined (SMD)
• For WCSP, the NSMD configuration is preferred due to its tighter control of the copper etch process and a reduction in the stress concentration points on the PCB side compared to the SMD configuration.
• A copper layer of less than or equal to 1 oz. is recommended to achieve higher solder join stand-off.  Greater than 1 oz. of copper thickness causes a lower effective solder joint stand-off, which may adversely impact solder joint reliability.
• For the NSMD configuration, the trace width at the connection to the land pad should not exceed 66 percent of the pad diameter.