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低壓側驅動器

UCC27512

現行

採用 SON 封裝且具 5-V UVLO 與分離輸出的 4-A/8-A 單通道閘極驅動器

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產品規格表

UCC27512

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 1 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 8 Input supply voltage (min) (V) 4.5 Input supply voltage (max) (V) 18 Features Hysteretic Logic Operating temperature range (°C) -40 to 140 Rise time (ns) 9 Fall time (ns) 7 Propagation delay time (µs) 0.013 Input threshold CMOS, TTL Channel input logic Inverting, Non-Inverting Input negative voltage (V) 0 Rating Catalog Undervoltage lockout (typ) (V) 4 Driver configuration Inverting, Non-Inverting
Number of channels 1 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 8 Input supply voltage (min) (V) 4.5 Input supply voltage (max) (V) 18 Features Hysteretic Logic Operating temperature range (°C) -40 to 140 Rise time (ns) 9 Fall time (ns) 7 Propagation delay time (µs) 0.013 Input threshold CMOS, TTL Channel input logic Inverting, Non-Inverting Input negative voltage (V) 0 Rating Catalog Undervoltage lockout (typ) (V) 4 Driver configuration Inverting, Non-Inverting
WSON (DRS) 6 9 mm² 3 x 3
  • Low-Cost Gate-Driver Device Offering Superior
    Replacement of NPN and PNP Discrete Solutions
  • 4-A Peak Source and 8-A Peak Sink Asymmetrical
    Drive
  • Strong Sink Current Offers Enhanced Immunity
    Against Miller Turnon
  • Split Output Configuration (Allows Easy and
    Independent Adjustment of Turnon and Turnoff
    Speeds) in the UCC27511 Saves 1 Diode
  • Fast Propagation Delays (13-ns Typical)
  • Fast Rise and Fall Times (9-ns and 7-ns Typical)
  • 4.5-V to 18-V Single Supply Range
  • Outputs Held Low During VDD UVLO (Ensures
    Glitch-Free Operation at Power Up and Power
    Down)
  • TTL and CMOS Compatible Input-Logic Threshold
    (Independent of Supply Voltage)
  • Hysteretic-Logic Thresholds for High-Noise
    Immunity
  • Dual-Input Design (Choice of an Inverting
    (IN– Pin) or Noninverting (IN+ Pin)
    Driver Configuration)
    • Unused Input Pin can be Used for Enable or
      Disable Function
  • Output Held Low When Input Pins Are Floating
  • Input Pin Absolute Maximum Voltage Levels Not
    Restricted by VDD Pin Bias Supply Voltage
  • Operating Temperature Range of –40°C
    to 140°C
  • 6-Pin DBV (SOT-23) and 6-Pin DRS (3-mm ×
    3-mm WSON With Exposed Thermal Pad) Package
    Options
  • Low-Cost Gate-Driver Device Offering Superior
    Replacement of NPN and PNP Discrete Solutions
  • 4-A Peak Source and 8-A Peak Sink Asymmetrical
    Drive
  • Strong Sink Current Offers Enhanced Immunity
    Against Miller Turnon
  • Split Output Configuration (Allows Easy and
    Independent Adjustment of Turnon and Turnoff
    Speeds) in the UCC27511 Saves 1 Diode
  • Fast Propagation Delays (13-ns Typical)
  • Fast Rise and Fall Times (9-ns and 7-ns Typical)
  • 4.5-V to 18-V Single Supply Range
  • Outputs Held Low During VDD UVLO (Ensures
    Glitch-Free Operation at Power Up and Power
    Down)
  • TTL and CMOS Compatible Input-Logic Threshold
    (Independent of Supply Voltage)
  • Hysteretic-Logic Thresholds for High-Noise
    Immunity
  • Dual-Input Design (Choice of an Inverting
    (IN– Pin) or Noninverting (IN+ Pin)
    Driver Configuration)
    • Unused Input Pin can be Used for Enable or
      Disable Function
  • Output Held Low When Input Pins Are Floating
  • Input Pin Absolute Maximum Voltage Levels Not
    Restricted by VDD Pin Bias Supply Voltage
  • Operating Temperature Range of –40°C
    to 140°C
  • 6-Pin DBV (SOT-23) and 6-Pin DRS (3-mm ×
    3-mm WSON With Exposed Thermal Pad) Package
    Options

The UCC27511 and UCC27512 single-channel, high-speed, low-side gate-driver device can effectively drive MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, UCC27511 and UCC27512 are capable of sourcing and sinking high peak-current pulses into capacitive loads offering rail-to-rail drive capability and extremely small propagation delay, typically 13 ns.

UCC27511 features a dual-input design which offers flexibility of implementing both inverting (IN– pin) and noninverting (IN+ pin) configuration with the same device. Either IN+ or IN– pin can be used to control the state of the driver output. The unused input pin can be used for enable and disable functions. For safety purpose, internal pullup and pulldown resistors on the input pins ensure that outputs are held low when input pins are in floating condition. Hence the unused input pin is not left floating and must be properly biased to ensure that driver output is in enabled for normal operation.

The input pin threshold of the UCC27511 device is based on TTL and CMOS-compatible low-voltage logic which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.

The UCC27511 and UCC27512 provides 4-A source, 8-A sink (asymmetrical drive) peak-drive current capability. Strong sink capability in asymmetrical drive boosts immunity against parasitic, Miller turnon effect. The UCC27511 device also features a unique split output configuration where the gate-drive current is sourced through OUTH pin and sunk through OUTL pin. This unique pin arrangement allows the user to apply independent turnon and turnoff resistors to the OUTH and OUTL pins respectively and easily control the switching slew rates.

UCC27511 and UCC27512 are designed to operate over a wide VDD range of 4.5 to 18 V and wide temperature range of –40°C to 140°C. Internal Undervoltage Lockout (UVLO) circuitry on VDD pin holds output low outside VDD operating range. The capability to operate at low voltage levels such as below 5 V, along with best-in-class switching characteristics, is especially suited for driving emerging wide band-gap power-switching devices such as GaN power-semiconductor devices.

The UCC27511 and UCC27512 single-channel, high-speed, low-side gate-driver device can effectively drive MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, UCC27511 and UCC27512 are capable of sourcing and sinking high peak-current pulses into capacitive loads offering rail-to-rail drive capability and extremely small propagation delay, typically 13 ns.

UCC27511 features a dual-input design which offers flexibility of implementing both inverting (IN– pin) and noninverting (IN+ pin) configuration with the same device. Either IN+ or IN– pin can be used to control the state of the driver output. The unused input pin can be used for enable and disable functions. For safety purpose, internal pullup and pulldown resistors on the input pins ensure that outputs are held low when input pins are in floating condition. Hence the unused input pin is not left floating and must be properly biased to ensure that driver output is in enabled for normal operation.

The input pin threshold of the UCC27511 device is based on TTL and CMOS-compatible low-voltage logic which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.

The UCC27511 and UCC27512 provides 4-A source, 8-A sink (asymmetrical drive) peak-drive current capability. Strong sink capability in asymmetrical drive boosts immunity against parasitic, Miller turnon effect. The UCC27511 device also features a unique split output configuration where the gate-drive current is sourced through OUTH pin and sunk through OUTL pin. This unique pin arrangement allows the user to apply independent turnon and turnoff resistors to the OUTH and OUTL pins respectively and easily control the switching slew rates.

UCC27511 and UCC27512 are designed to operate over a wide VDD range of 4.5 to 18 V and wide temperature range of –40°C to 140°C. Internal Undervoltage Lockout (UVLO) circuitry on VDD pin holds output low outside VDD operating range. The capability to operate at low voltage levels such as below 5 V, along with best-in-class switching characteristics, is especially suited for driving emerging wide band-gap power-switching devices such as GaN power-semiconductor devices.
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UCC27614 現行 30V VDD, 10A/10A single-channel low-side driver with 4V UVLO and low propagation delay Non-inverting single-channel driver with Increased VDD and Current rating

技術文件

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類型 標題 日期
* Data sheet UCC2751x Single-Channel, High-Speed, Low-Side Gate Driver (With 4-A Peak Source and 8-A Peak Sink) datasheet (Rev. F) PDF | HTML 2013年 12月 9日
Application note Review of Different Power Factor Correction (PFC) Topologies' Gate Driver Needs PDF | HTML 2024年 1月 22日
Application note Using a Single-Output Gate-Driver for High-Side or Low-Side Drive (Rev. B) PDF | HTML 2023年 9月 8日
Application note Benefits of a Compact, Powerful, and Robust Low-Side Gate Driver PDF | HTML 2021年 11月 10日
Application brief External Gate Resistor Selection Guide (Rev. A) 2020年 2月 28日
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 2020年 2月 28日
Application brief How to overcome negative voltage transients on low-side gate drivers' inputs 2019年 1月 18日
More literature Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) 2018年 10月 29日
Application brief Enable Function with Unused Differential Input 2018年 7月 11日
Selection guide Power Management Guide 2018 (Rev. R) 2018年 6月 25日
Application brief Low-Side Gate Drivers With UVLO Versus BJT Totem-Pole 2018年 3月 16日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬型號

UCC27512 PSpice Transient Model (Rev. B)

SLUM316B.ZIP (50 KB) - PSpice Model
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模擬型號

UCC27512 TINA-TI Transient Model

SLUM442.ZIP (9 KB) - TINA-TI Spice Model
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模擬型號

UCC27512 TINA-TI Transient Reference Design

SLUM441.TSC (74 KB) - TINA-TI Reference Design
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模擬型號

UCC27512 Unencrypted PSpice Transient Model

SLUM489.ZIP (2 KB) - PSpice Model
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計算工具

SLURB27 — UCC27511 and UCC27512 Schematic Review Template

Design reference and reference for the UCC27511 and the UCC27512 to assist in system design.
支援產品和硬體

支援產品和硬體

產品
低壓側驅動器
UCC27511 — 具 5V UVLO、分離輸出和 13-ns Prop 延遲的 4-A/8-A 單通道閘極驅動器 UCC27512 — 採用 SON 封裝且具 5-V UVLO 與分離輸出的 4-A/8-A 單通道閘極驅動器 UCC27511A — 具有 5V UVLO、分離輸出、5V 輸入電壓處理能力的 4A/8A 單通道閘極驅動器 UCC27511A-Q1 — Automotive 20V VDD, 4A/8A single-channel driver with 5V UVLO and split outputs
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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一，涵蓋我們的類比和電源產品組合，以及特定類比行為模型，且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。 

在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
要求
參考設計

PMP22089 — 具有 GAN 技術的半橋負載點轉換器參考設計

此參考設計修改內側變壓器匝數比，從 5:1 修改至 3:1，以縮小輸入範圍。電路板支援 24V 至 32V 的輸入電壓以及 0.5V 至 1.0V 的輸出電壓，輸出電流高達 40A。 此拓撲可有效支援高降壓比，同時提供顯著的輸出電流和可控性。原始 EVM 的設計旨在評估 LMG5200 GaN 半橋功率級和 TPS53632G 半橋負載點 (PoL) 控制器。此電路板可將轉換器當成具有倍流整流器的單級硬切換半橋使用。  此電路板是 LMG5200POLEVM-10 評估模組的重新設計。
Test report: PDF
電路圖: PDF
參考設計

PMP4497 — LMG5200 48V 轉 1V/40A 單段式轉換器參考設計

PMP4497 是一款基於 GaN 的參考設計解決方案，適用於 FPGA 與 ASIC 等應用的 Vcore 供電。採用高整合度與低開關損耗設計的 GaN 模組 LMG5200，可實現從 48V 至 1.0V 的高效率單級解決方案，取代傳統兩級架構。此設計展現了 GaN 的性能表現與系統優勢，並與傳統兩級解決方案進行對比。  電路板上嵌入了一款低成本 ER18 平面 PCB 變壓器。此設計以精巧外型尺寸 (45mm*26mm*11mm) 實現完整功能。透過最佳化工作頻率與元件，可進一步縮小整體尺寸。
Test report: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
WSON (DRS) 6 Ultra Librarian
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  • 認證摘要
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