The DAC39J82 is a very low power, 16-bit, dual-channel, 2.8 GSPS digital to analog converter (DAC) with JESD204B interface. The maximum input data rate is 1.4 GSPS.
Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.
The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement.
A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.
DAC39J82 provides four analog outputs, and the data from the internal two digital paths can be routed to any two out of these four DAC outputs via the output multiplexer.
| 重要文件 | 類型 | 標題 | 格式選項 | 日期 |
|---|---|---|---|---|
| * | Data sheet | DAC39J82 Dual-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface datasheet | PDF | HTML | 2015年 1月 26日 |
| Application note | DAC3xJ8x Device Initialization and SYSREF Configuration | 2017年 9月 27日 | ||
| Application note | System solution for avionics & defense | 2015年 9月 23日 |
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DAC39J82EVM 是評估模組 (EVM)，其設計旨在評估 DAC39J82EVM 高速 JESD204B 介面 DAC。EVM 包括板載計時解決方案 (LMK04828)、變壓器耦合輸出、完整電源解決方案，以及易於使用的軟體 GUI 和 USB 介面。
DAC39J82EVM 旨在與德州儀器的 JESD204B 模式產生器卡 TSW14J56EVM 無縫合作，其透過高速數據轉換器 Pro (HSDCPro) 軟體工具進行高速數據轉換器評估。DAC3XJ8XEVM 也設計來與包含 FMC 連接器的一流 FPGA 廠商的許多開發套件搭配使用。
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
針對此類多天線發射器的實作，每個獨立的發射器都需要數位類比轉換器 (DAC) 來將數位位元轉換為射頻訊號。多個發射器與其相關的天線也必須在時間上同步。此設計可採用 JESD204B (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCCSP (AAV) | 144 | Ultra Librarian |
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。