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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC12DJ5200-SEP

現行

耐受輻射保、30-krad、12 位元、雙 5.2-GSPS 或單 10.4-GSPS ADC

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產品規格表

ADC12DJ5200-SEP

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 5200, 10400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 7900 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.825 Power consumption (typ) (mW) 4000 Architecture Folding Interpolating SNR (dB) 55.6 ENOB (Bits) 8.8 SFDR (dB) 65 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 30 Radiation, SEL (MeV·cm2/mg) 43
Sample rate (max) (Msps) 5200, 10400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 7900 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.825 Power consumption (typ) (mW) 4000 Architecture Folding Interpolating SNR (dB) 55.6 ENOB (Bits) 8.8 SFDR (dB) 65 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 30 Radiation, SEL (MeV·cm2/mg) 43
FCCSP (ALR) 144 100 mm² 10 x 10
  • Radiation Tolerance:
    • Total Ionizing Dose (TID): 30krad (Si)
    • Single Event Latchup (SEL): 43 MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Space-enhanced plastic (space EP):
    • Meets ASTM E595 out-gassing specification
    • Vendor item drawing (VID) V62/22611
    • Temperature range: –55°C to 125°C
    • One fabrication, assembly, and test site
    • Wafer lot traceability
    • Extended product life cycle
    • Extended product change notification
  • ADC core:
    • 12-bit resolution
    • Up to 10.4GSPS in single-channel mode
    • Up to 5.2GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (–20dBFS, VFS = 1VPP-DIFF):
      • Dual-channel mode: –151.8dBFS/Hz
      • Single-channel mode: –154.4dBFS/Hz
    • ENOB (dual channel, FIN = 2.4GHz): 8.6 Bits
  • Buffered analog inputs with VCMI of 0V:
    • Analog input bandwidth (–3dB): 8GHz
    • Usable input frequency range: > 10GHz
    • Full-scale input voltage (VFS, default): 0.8VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19-fs Step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Time stamp for sample marking
  • JESD204C serial data interface:
    • Maximum lane rate: 17.16Gbps
    • Support for 64b/66b and 8b/10b encoding
    • 8b/10b modes are JESD204B compatible
  • Optional digital down-converters (DDC):
    • Complex decimation: 4x (IBW = 0.2*FS = 2.08GHz in DES mode, 1.04GHz per channel in dual channel mode), 8x, 16x and 32x
    • Four independent 32-Bit NCOs per DDC
  • Peak RF Input Power (Diff): +26.5dBm (+ 27.5dBFS, 560x fullscale power)
  • Programmable FIR filter for equalization
  • Power consumption: 4W
  • Power supplies: 1.1V, 1.9V
  • Radiation Tolerance:
    • Total Ionizing Dose (TID): 30krad (Si)
    • Single Event Latchup (SEL): 43 MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Space-enhanced plastic (space EP):
    • Meets ASTM E595 out-gassing specification
    • Vendor item drawing (VID) V62/22611
    • Temperature range: –55°C to 125°C
    • One fabrication, assembly, and test site
    • Wafer lot traceability
    • Extended product life cycle
    • Extended product change notification
  • ADC core:
    • 12-bit resolution
    • Up to 10.4GSPS in single-channel mode
    • Up to 5.2GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (–20dBFS, VFS = 1VPP-DIFF):
      • Dual-channel mode: –151.8dBFS/Hz
      • Single-channel mode: –154.4dBFS/Hz
    • ENOB (dual channel, FIN = 2.4GHz): 8.6 Bits
  • Buffered analog inputs with VCMI of 0V:
    • Analog input bandwidth (–3dB): 8GHz
    • Usable input frequency range: > 10GHz
    • Full-scale input voltage (VFS, default): 0.8VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19-fs Step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Time stamp for sample marking
  • JESD204C serial data interface:
    • Maximum lane rate: 17.16Gbps
    • Support for 64b/66b and 8b/10b encoding
    • 8b/10b modes are JESD204B compatible
  • Optional digital down-converters (DDC):
    • Complex decimation: 4x (IBW = 0.2*FS = 2.08GHz in DES mode, 1.04GHz per channel in dual channel mode), 8x, 16x and 32x
    • Four independent 32-Bit NCOs per DDC
  • Peak RF Input Power (Diff): +26.5dBm (+ 27.5dBFS, 560x fullscale power)
  • Programmable FIR filter for equalization
  • Power consumption: 4W
  • Power supplies: 1.1V, 1.9V

The ADC12DJ5200-SEP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10GHz. ADC12DJ5200-SEP can be configured as a dual-channel, 5.2GSPS ADC or single-channel, 10.4GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ5200-SEP uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multichannel applications. Optional digital down converters (DDCs) are available to provide digital conversion to base-band and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.

The ADC12DJ5200-SEP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10GHz. ADC12DJ5200-SEP can be configured as a dual-channel, 5.2GSPS ADC or single-channel, 10.4GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ5200-SEP uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multichannel applications. Optional digital down converters (DDCs) are available to provide digital conversion to base-band and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.
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類型 標題 日期
* Data sheet ADC12DJ5200-SEP 10.4GSPS Single-Channel or 5.2GSPS Dual-Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. A) PDF | HTML 2025年 4月 8日
* Radiation & reliability report ADC12DJ5200-SEP Production Flow and Reliability Report (Rev. A) PDF | HTML 2025年 3月 12日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

ADC12DJ5200RFEVM — ADC12DJ5200RF 射頻取樣 12 位元雙通道 5.2GSPS 或單通道 10.4GSPS ADC 評估模組

ADC12DJ5200RF 評估模組 (EVM) 專為評估 ADC12DJ5200RF 系列高速類比轉數位轉換器 (ADC) 所設計。本 EVM 搭載 ADC12DJ5200RF 晶片，該晶片為具備 JESD204B 介面的 12 位元、雙通道 5.2GSPS 或單通道 10.4GSPS ADC，可評估該系列所有解析度與取樣率的裝置。
使用指南: PDF | HTML
View Options
模擬型號

ADC12DJ5200RF IBIS and IBIS-AMI Model (Rev. A)

SLVMD65A.ZIP (49879 KB) - IBIS-AMI Model
下載
模擬型號

ADC12DJ5200RF S-Parameter Model

SLVMDX5.ZIP (1563 KB) - S-Parameter Model
下載
計算工具

ADC12DJ5200RF-CALC — ADC12DJ5200RF input network full-scale calculation tool.

Calculation tool referenced in application note SLVAFZ7.
支援產品和硬體

支援產品和硬體

產品
高速 ADC (≥10 MSPS)
ADC12DJ5200RF — 具有雙通道 5.2 GSPS 或單通道 10.4 GSPS 的射頻取樣 12 位元 ADC ADC12DJ4000RF — 具有 4-GSPS 雙通道或 8-GSPS 單通道的射頻取樣 12 位元 ADC ADC08DJ5200RF — 具雙通道 5.2 GSPS 或單通道 10.4 GSPS 的 RF 取樣 8 位元 ADC ADC12DJ5200-EP — 具有雙通道 5.2 GSPS 或單通道 10.4 GSPS 的強化型產品 12 位元 ADC ADC12DJ5200-SEP — 耐受輻射保、30-krad、12 位元、雙 5.2-GSPS 或單 10.4-GSPS ADC ADC12DJ5200-SP — 抗輻射保證 (RHA)、300-krad、12 位元、雙 5.2-GSPS 或單 10.4-GSPS ADC
硬體開發
開發板
ADC12DJ5200RFEVM — ADC12DJ5200RF 射頻取樣 12 位元雙通道 5.2GSPS 或單通道 10.4GSPS ADC 評估模組
下載
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一，涵蓋我們的類比和電源產品組合，以及特定類比行為模型，且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。 

在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
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參考設計

TIDA-010274 — 航太級離散式 RF 取樣收發器參考設計

此參考設計整合了一個 10 GSPS 雙數位轉類比轉換器和一個 5 GSPS 雙類比轉數位轉換器，RF 介面上有主動式平衡不平衡轉換器，支援 X 頻帶。此設計還整合了航太級時脈子卡和航太級電源解決方案子卡。
Design guide: PDF
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FCCSP (ALR) 144 Ultra Librarian
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