ADC12DJ5200-SEP
- Radiation Tolerance:
- Total Ionizing Dose (TID): 30krad (Si)
- Single Event Latchup (SEL): 43 MeV-cm2/mg
- Single Event Upset (SEU) immune registers
- Space-enhanced plastic (space EP):
- Meets ASTM E595 out-gassing specification
- Vendor item drawing (VID) V62/22611
- Temperature range: –55°C to 125°C
- One fabrication, assembly, and test site
- Wafer lot traceability
- Extended product life cycle
- Extended product change notification
- ADC core:
- 12-bit resolution
- Up to 10.4GSPS in single-channel mode
- Up to 5.2GSPS in dual-channel mode
- Performance specifications:
- Noise floor (–20dBFS, VFS =
1VPP-DIFF):
- Dual-channel mode: –151.8dBFS/Hz
- Single-channel mode: –154.4dBFS/Hz
- ENOB (dual channel, FIN = 2.4GHz): 8.6 Bits
- Noise floor (–20dBFS, VFS =
1VPP-DIFF):
- Buffered analog inputs with VCMI of
0V:
- Analog input bandwidth (–3dB): 8GHz
- Usable input frequency range: > 10GHz
- Full-scale input voltage (VFS, default): 0.8VPP
- Noiseless aperture delay (tAD) adjustment:
- Precise sampling control: 19-fs Step
- Simplifies synchronization and interleaving
- Temperature and voltage invariant delays
- Easy-to-use synchronization features:
- Automatic SYSREF timing calibration
- Time stamp for sample marking
- JESD204C serial data interface:
- Maximum lane rate: 17.16Gbps
- Support for 64b/66b and 8b/10b encoding
- 8b/10b modes are JESD204B compatible
- Optional digital down-converters (DDC):
- Complex decimation: 4x (IBW = 0.2*FS = 2.08GHz in DES mode, 1.04GHz per channel in dual channel mode), 8x, 16x and 32x
- Four independent 32-Bit NCOs per DDC
- Peak RF Input Power (Diff): +26.5dBm (+ 27.5dBFS, 560x fullscale power)
- Programmable FIR filter for equalization
- Power consumption: 4W
- Power supplies: 1.1V, 1.9V
The ADC12DJ5200-SEP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10GHz. ADC12DJ5200-SEP can be configured as a dual-channel, 5.2GSPS ADC or single-channel, 10.4GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
The ADC12DJ5200-SEP uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.
Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multichannel applications. Optional digital down converters (DDCs) are available to provide digital conversion to base-band and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADC12DJ5200-SEP 10.4GSPS Single-Channel or 5.2GSPS Dual-Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. A) | PDF | HTML | 2025/4/8 | ||
| * | 輻射及可靠性報告 | ADC12DJ5200-SEP Production Flow and Reliability Report (Rev. A) | PDF | HTML | 2025/3/12 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
ADC12DJ5200RFEVM — ADC12DJ5200RF 射頻取樣 12 位元雙通道 5.2GSPS 或單通道 10.4GSPS ADC 評估模組
ADC12DJ5200RF-CALC — ADC12DJ5200RF 輸入網路全刻度計算工具。
TIDA-010274 — 航太級離散式 RF 取樣收發器參考設計
此參考設計整合了一個 10 GSPS 雙數位轉類比轉換器和一個 5 GSPS 雙類比轉數位轉換器，RF 介面上有主動式平衡不平衡轉換器，支援 X 頻帶。此設計還整合了航太級時脈子卡和航太級電源解決方案子卡。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCCSP (ALR) | 144 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。