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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC08DJ5200RF

現行

具雙通道 5.2 GSPS 或單通道 10.4 GSPS 的 RF 取樣 8 位元 ADC

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產品規格表

ADC08DJ5200RF

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 5200, 10400 Resolution (Bits) 8 Number of input channels 1, 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 8100 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.825 Power consumption (typ) (mW) 3700 Architecture Folding Interpolating SNR (dB) 48.8 ENOB (Bits) 7.8 SFDR (dB) 65 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 5200, 10400 Resolution (Bits) 8 Number of input channels 1, 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 8100 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.825 Power consumption (typ) (mW) 3700 Architecture Folding Interpolating SNR (dB) 48.8 ENOB (Bits) 7.8 SFDR (dB) 65 Operating temperature range (°C) -40 to 85 Input buffer Yes
FCCSP (AAV) 144 100 mm² 10 x 10
  • ADC core:
    • 8-bit resolution
    • Up to 10.4GSPS in single-channel mode
    • Up to 5.2GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (–20dBFS, VFS = 1 VPP-DIFF):
      • Dual-channel mode: –143.4dBFS/Hz
      • Single-channel mode: –146.2dBFS/Hz
    • ENOB (dual channel, FIN = 2.4GHz, TYP): 7.8 Bits
  • Buffered analog inputs with VCMI of 0V:
    • Analog input bandwidth (–3dB): 8.1GHz
    • Usable input frequency range: > 10GHz
    • Full-scale input voltage (VFS, default): 0.8VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19fs Step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204C serial data interface:
    • Maximum lane rate: 17.16Gbps
    • Support for 64b/66b and 8b/10b encoding
    • 8b/10b modes are JESD204B compatible
  • Peak RF Input Power (Diff): +26.5dBm (+ 27.5dBFS, 560x fullscale power)
  • Programmable FIR filter for equalization
  • Power consumption: 3.8W
  • Power supplies: 1.1V, 1.9V
  • ADC core:
    • 8-bit resolution
    • Up to 10.4GSPS in single-channel mode
    • Up to 5.2GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (–20dBFS, VFS = 1 VPP-DIFF):
      • Dual-channel mode: –143.4dBFS/Hz
      • Single-channel mode: –146.2dBFS/Hz
    • ENOB (dual channel, FIN = 2.4GHz, TYP): 7.8 Bits
  • Buffered analog inputs with VCMI of 0V:
    • Analog input bandwidth (–3dB): 8.1GHz
    • Usable input frequency range: > 10GHz
    • Full-scale input voltage (VFS, default): 0.8VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19fs Step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204C serial data interface:
    • Maximum lane rate: 17.16Gbps
    • Support for 64b/66b and 8b/10b encoding
    • 8b/10b modes are JESD204B compatible
  • Peak RF Input Power (Diff): +26.5dBm (+ 27.5dBFS, 560x fullscale power)
  • Programmable FIR filter for equalization
  • Power consumption: 3.8W
  • Power supplies: 1.1V, 1.9V

The ADC08DJ5200RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that directly samples input frequencies from DC to above 10GHz. The ADC08DJ5200RF can be configured as a dual-channel, 5.2GSPS ADC or single-channel, 10.4GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC08DJ5200RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. A programmable FIR filter allows on-chip equalization.

The ADC08DJ5200RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that directly samples input frequencies from DC to above 10GHz. The ADC08DJ5200RF can be configured as a dual-channel, 5.2GSPS ADC or single-channel, 10.4GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC08DJ5200RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. A programmable FIR filter allows on-chip equalization.
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重要文件 類型 標題 格式選項 日期
* Data sheet ADC08DJ5200RF 10.4GSPS Single-Channel or 5.2GSPS Dual-Channel, 8-bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. B) PDF | HTML 2025年 4月 8日
Application note Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends PDF | HTML 2025年 3月 28日
Application note Evaluating High-Speed, RF ADC Converter Front-end Architectures PDF | HTML 2025年 3月 26日

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ADC08DJ5200RFEVM — 具有雙路 5.2 GSPS 或單路 GSPS-10.4 且適用於射頻取樣 8 位元 ADC 的 ADC08DJ5200RF 評估模組

ADC08DJ5200RF 評估模組 (EVM) 是用於評估 ADC08DJ5200RF 的平台。ADC08DJ5200RF 是一款低功耗、8 位元、雙通道 5.2-GSPS 或單通道 10.4-GSPS 的射頻取樣類比轉數位轉換器 (ADC)，具有緩衝類比輸入、整合式數位降壓轉換器與 JESD204B/C 介面。此 EVM 具有變壓器耦合類比輸入，可適應廣泛的訊號來源和頻率。

ADC08DJ5200RFEVM 隨附 LMX2594 時脈合成器和 LMK04828 JESD204B/C 時脈產生器，可配置成提供適何完整 JESD204B/C 子類別 1 時脈解決方案的超低抖動 ADC (...)

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TI204C-IP — Request for JESD204 rapid design IP

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

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計算工具

ADC12DJ5200RF-CALC — ADC12DJ5200RF input network full-scale calculation tool.

Calculation tool referenced in application note SLVAFZ7.
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FCCSP (AAV) 144 Ultra Librarian
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