TPS51622
- Intel© Serial VID (SVID) Compliant
- 1- or 2-Phase Operation
- Full VR12.6 Mobile Feature Set Including Digital Current
Monitor, PS3 and PS4 Operation - 8-Bit DAC with 0.50-V to 2.30-V Output Range
- Optimized Efficiency at Light and Heavy Loads
- 8 Independent Levels of Overshoot Reduction (OSR)
and Undershoot Reduction (USR) - Driverless Configuration for Efficient High-Frequency
Switching - Supports Discrete, Power Block, PowerStage or
DrMOS MOSFET Implementations - Accurate, Adjustable Voltage Positioning
- 300-kHz to 1-MHz Frequency Selections
- Patented AutoBalance Phase Balancing
- Selectable 8-level Current Limit
- 4.5-V to 28-V Conversion Voltage Range
- Small, 4 × 4, 32-Pin, QFN PowerPad Package
The TPS51622A is a driverless, fully SVID compliant, VR12.6 step-down controller. Advanced control features such as D-CAP+ architecture with overlapping pulse support undershoot reduction (USR) and overshoot reduction (OSR) provide fast transient response, lowest output capacitance and high efficiency. The TPS51622A also supports single-phase operation in CCM or DCM for light-load efficiency. The TPS51622A integrates the full complement of VR12.6 I/O features including VR_READY (PGOOD), ALERT and VR_HOT. The SVID interface address allows programming from 0 to 7. In PS4, the quiescent power consumption of controller is typical 0.25 mW. Adjustable control of VCPU slew rate and voltage positioning round out the VR12.6 features. Paired with the new TPS51604 FET gate driver, the solution delivers exceptionally high speed and low switching loss. The TPS51622A works with selected TI Power Stage™ products for optimum efficiency as well as DrMOS products.
The TPS51622A package is a space saving, thermally enhanced 32-pin QFN that operates from –40°C to 105°C.
特别说明
如需获取详细的数据表和其他设计支持工具，请发送电子邮件至 IMVP@list.ti.com。
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | 2-Phase, D-CAP+™ Step-Down Controller for VR12.6 Vcpu 数据表 (Rev. A) | 2013-7-17 | |||
| 技术文章 | How to reduce acoustic noise of MLCCs in power applications | PDF | HTML | 2016-8-9 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VQFN (RSM) | 32 | Ultra Librarian |