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SN74LVC8T245-EP

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具有可配置电压转换和三态输出的 8 位双电源总线收发器（增强型产品）

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SN74LVC8T245-EP

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产品详情

Bits (#) 8 Data rate (max) (Mbps) 200 Topology Push-Pull Vin (min) (V) 1.65 Vin (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Applications GPIO, JTAG, SPI, UART Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Prop delay (ns) 10.9 Technology family LVC Supply current (max) (mA) 0.025 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
Bits (#) 8 Data rate (max) (Mbps) 200 Topology Push-Pull Vin (min) (V) 1.65 Vin (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Applications GPIO, JTAG, SPI, UART Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Prop delay (ns) 10.9 Technology family LVC Supply current (max) (mA) 0.025 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
SOIC (DW) 24 159.65 mm² (15.5 mm × 10.3 mm) TSSOP (PW) 24 49.92 mm² (7.8 mm × 6.4 mm) VQFN (RHL) 24 19.25 mm² (5.5 mm × 3.5 mm)
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • VCC Isolation Feature – If Either VCC Input Is at GND, All Are in the High-Impedance State
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • VCC Isolation Feature – If Either VCC Input Is at GND, All Are in the High-Impedance State
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This 8-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74LVC8T245-EP is optimized to operate with VCCA and VCCB set at 1.65 V to 5.5 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5.5-V voltage nodes.

The SN74LVC8T245-EP is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74LVC8T245-EP is designed so that the control pins (DIR and OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, all outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This 8-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74LVC8T245-EP is optimized to operate with VCCA and VCCB set at 1.65 V to 5.5 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5.5-V voltage nodes.

The SN74LVC8T245-EP is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74LVC8T245-EP is designed so that the control pins (DIR and OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, all outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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技术文档

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 SN74LVC8T245-EP 8-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and Tri-State Outputs 数据表 (Rev. A) PDF | HTML 2017-3-2
* 辐射与可靠性报告 CLVC1G126IDCKREP Reliability Report 2018-1-25
* 辐射与可靠性报告 SN74LVC8T245MPWREP Reliability Report 2015-2-6
* 辐射与可靠性报告 SN74LVC8T245MPWREP Reliability Report 2011-8-31
* VID SN74LVC8T245-EP VID V6209615 2016-6-21
应用手册 原理图检查清单 - 使用自动双向转换器进行设计的指南 PDF | HTML 英语版 PDF | HTML 2024-12-3
应用手册 原理图检查清单 - 使用固定或方向控制转换器进行设计的指南 PDF | HTML 英语版 PDF | HTML 2024-10-3
应用手册 Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024-7-3
应用简报 Voltage Translation for Rugged High Reliability Applications PDF | HTML 2021-7-20
选择指南 Voltage Translation Buying Guide (Rev. A) 2021-4-15

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SN74LVC8T245 IBIS Model

SCEM494.ZIP (56 KB) - IBIS 模型
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SOIC (DW) 24 Ultra Librarian
TSSOP (PW) 24 Ultra Librarian
VQFN (RHL) 24 Ultra Librarian
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