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SN74LVC86A-EP

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增强型产品 4 通道、2 输入、2V 至 3.6V XOR（异或）门

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SN74LVC86A-EP

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产品详情

Technology family LVC Number of channels 4 Inputs per channel 2 IOL (max) (mA) 24 Input type Standard CMOS IOH (max) (mA) -24 Output type Push-Pull Features High speed (tpd 10-50ns) Data rate (max) (Mbps) 100 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
Technology family LVC Number of channels 4 Inputs per channel 2 IOL (max) (mA) 24 Input type Standard CMOS IOH (max) (mA) -24 Output type Push-Pull Features High speed (tpd 10-50ns) Data rate (max) (Mbps) 100 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm) TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm)
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –40°C to 125°C and –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Operates From 2 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.6 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –40°C to 125°C and –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Operates From 2 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.6 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

The SN74LVC86A quadruple 2-input exclusive-OR gate is designed for 2.7-V to 3.6-V VCC operation.

The device performs the Boolean function Y = A B or Y = AB + AB in positive logic.

A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

The SN74LVC86A quadruple 2-input exclusive-OR gate is designed for 2.7-V to 3.6-V VCC operation.

The device performs the Boolean function Y = A B or Y = AB + AB in positive logic.

A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 SN74LVC86A-EP 数据表 (Rev. B) 2007-7-25
* 辐射与可靠性报告 SN74LVC86AMDREP Reliability Report 2011-10-5
* 辐射与可靠性报告 SN74LVC86AQDREP Reliability Report 2011-10-5
* VID SN74LVC86A-EP VID V6204670 2016-6-21

设计与开发

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封装 引脚 CAD 符号、封装和 3D 模型
SOIC (D) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

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