主页 逻辑和电压转换 缓冲器、驱动器和收发器 通用收发器
主页
逻辑和电压转换
缓冲器、驱动器和收发器
通用收发器

SN74ALVCH245

正在供货

具有三态输出的八通道总线收发器

立即订购
数据表

SN74ALVCH245

正在供货
数据表 立即订购

产品详情

Number of channels 8 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type LVTTL Output type LVTTL Features Balanced outputs, Bus-hold, Ultra high speed (tpd <5ns) Technology family ALVC Rating Catalog Operating temperature range (°C) -40 to 85
Number of channels 8 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type LVTTL Output type LVTTL Features Balanced outputs, Bus-hold, Ultra high speed (tpd <5ns) Technology family ALVC Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm) TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm) TVSOP (DGV) 20 32 mm² (5 mm × 6.4 mm)
  • Operates From 1.65 V to 3.6 V
  • Max tpd of 3.4 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Operates From 1.65 V to 3.6 V
  • Max tpd of 3.4 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

This octal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so the buses are effectively isolated.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This octal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so the buses are effectively isolated.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
filter 查找其他 通用收发器
下载 观看带字幕的视频 视频

您可能感兴趣的相似产品

open-in-new 比较替代产品
功能与比较器件相同且具有相同引脚。
SN74AC245 正在供货 具有三态输出的八路总线收发器 Voltage range 2V to 6V, average propagation delay 7ns, average drive strength 24mA
新 SN74LVC241A 正在供货 具有三态输出的 1.65V 至 3.6V 8 通道缓冲器 Voltage range 1.65V to 3.6V, average propagation delay 5.5ns, average drive strength 24mA

技术文档

未找到结果。请清除搜索并重试。
查看全部 2
顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 SN74ALVCH245 数据表 (Rev. G) 2004-8-20
应用手册 An Overview of Bus-Hold Circuit and the Applications (Rev. B) 2018-9-17

设计与开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

评估板

14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块

14-24-LOGIC-EVM 评估模块 (EVM) 设计用于支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。

用户指南: PDF | HTML
支持的产品和硬件
有库存
限制：
??asset.out-of-stock-ti_zh_CN??
无货
仿真模型

SN74ALVCH245 IBIS Model

SCEM209.ZIP (45 KB) - IBIS 模型
支持的产品和硬件
封装 引脚 CAD 符号、封装和 3D 模型
SOIC (DW) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian
TVSOP (DGV) 20 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

订购和质量

支持和培训

视频