SCANSTA111
- True IEEE 1149.1 Hierarchical and Multidrop Addressable Capability
- The 7 Slot Inputs Support Up to 121 Unique Addresses, an Interrogation Address, Broadcast Address, and 4 Multi-Cast Group Addresses (Address 000000 is Reserved)
- 3 IEEE 1149.1-Compatible Configurable Local Scan Ports
- Mode Register0 Allows Local TAPs to be Bypassed, Selected for Insertion Into the Scan Chain Individually, or Serially in Groups of Two or Three
- Transparent Mode can be Enabled with a Single Instruction to Conveniently Buffer the Backplane IEEE 1149.1 Pins to those on a Single Local Scan Port
- LSP ACTIVE Outputs Provide Local Port Enable Signals for Analog Busses Supporting IEEE 1149.4.
- General Purpose Local Port Pass-Through Bits are Useful for Delivering Write Pulses for FPGA Programming or Monitoring Device Status.
- Known Power-Up State
- TRST on All Local Scan Ports
- 32-Bit TCK Counter
- 16-Bit LFSR Signature Compactor
- Local TAPs can become TRI-STATE via the OE Input to Allow an Alternate Test Master to Take Control of the Local TAPs (LSP0-2 Have a TRI-STATE Notification Output)
- 3.0-3.6V VCC Supply Operation
- Power-Off High Impedance Inputs and Outputs
- Supports Live Insertion/Withdrawal
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The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANSTA111 supports up to 3 local IEEE 1149.1 scan rings which can be accessed individually or combined serially. Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | SCANSTA111 Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port 数据表 (Rev. K) | 2013-4-12 | |||
| 应用手册 | Simplified Programming of Altera FPGAs Using CSANSTA111/112 JTAG Scan Chain Mux (Rev. D) | 2013-4-26 | ||||
| 应用手册 | AN-1312 SCANSTA111/SCANSTA112 Scan Bridge Timing (Rev. B) | 2013-4-26 | ||||
| 应用手册 | AN-1259 SCANSTA112 Designer's Reference (Rev. H) | 2013-4-26 | ||||
| 应用手册 | Simplified Program of Xilinx Devices Using a SCANSTA111/112 JTAG Scan Chain Mux (Rev. C) | 2013-4-26 | ||||
| 应用手册 | Application Note 1259 SCANSTA112 Designer's Reference (cn) | 2011-3-28 | ||||
| 应用手册 | Application Note 1312 SCANSTA111/SCANSTA112 Scan Bridge Timing (cn) | 2010-6-7 | ||||
| 应用手册 | App Note 1340 Simp Prog of Xilinx Devs Using SCANSTA111/112 JTAG Scan Chain Mux | 2009-12-17 | ||||
| 应用手册 | JTAG Advanced Capabilities and System Design | 2009-3-19 | ||||
| 应用手册 | Partition IEEE 1149.1 SCAN Chains for Manageability! | 2003-3-6 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
EVF-WORKBENCH-CONVERTER-SW — EVF Workbench - Converts JTAG SVF to National’s EVF2 SCAN Format
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| NFBGA (NZA) | 49 | Ultra Librarian |
| TSSOP (DGG) | 48 | Ultra Librarian |
订购和质量
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