CDCU877A
- 1.8-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II) Applications
- Spread Spectrum Clock Compatible
- Operating Frequency: 10 MHz to 400 MHz
- Low Current Consumption: <135 mA
- Low Jitter (Cycle-Cycle): ±30 ps
- Low Output Skew: 35 ps
- Low Period Jitter: ±20 ps
- Low Dynamic Phase Offset: ±15 ps
- Low Static Phase Offset: ±50 ps
- Distributes One Differential Clock Input to Ten Differential Outputs
- 52-Ball µBGA (MicroStar™ Junior BGA, 0,65-mm pitch) and 40-Pin MLF
- External Feedback Pins (FBIN, FBIN) are Used to Synchronize the Outputs to the Input Clocks
- Meets or Exceeds JESD82-8 PLL Standard for PC2-3200/4300
- Fail-Safe Inputs
MicroStar is a trademark of Texas Instruments.
The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes.
When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time.
The CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from -40°C to 85°C.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | 1.8V Phase Lock Loop Clock Driver 数据表 (Rev. D) | 2007-7-5 | |||
| 用户指南 | CTS MicroStar BGA Discontinued and Redesigned | 2020-11-3 | ||||
| 应用手册 | DDR2 Memory Interface Clocks and Registers - Overview | 2009-3-25 | ||||
| 应用手册 | Application Examples for CDCUx877x PLL family | 2008-5-7 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VQFN (RHA) | 40 | Ultra Librarian |
| NFBGA (NMK) | 52 | Ultra Librarian |