CDCM7005-SP

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Radiation-hardened, QML-V, 3.3V high-performance clock jitter cleaner and synchronizer

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数据表

document-pdfAcrobat CDCM7005-SP 3.3-V High Performance Rad-Tolerant Class V, Clock Synchronizer and Jitter Cleaner 数据表 (Rev. G) (英语) PDF | HTML

CDCM7005-SP

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数据表

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产品详情

Number of input channels

2

Number of outputs

5

Features

Programmable Delay

Output frequency (min) (MHz)

0

Output frequency (max) (MHz)

1500

Output type

LVCMOS, LVPECL

Input type

LVCMOS (REF_CLK), LVPECL (VCXO_CLK)

Operating temperature range (°C)

-55 to 125

Number of input channels

2

Number of outputs

5

Features

Programmable Delay

Output frequency (min) (MHz)

0

Output frequency (max) (MHz)

1500

Output type

LVCMOS, LVPECL

Input type

LVCMOS (REF_CLK), LVPECL (VCXO_CLK)

Operating temperature range (°C)

-55 to 125

CFP (HFG)

52

363.474225 mm² (0 mm × 0 mm)

High Performance LVPECL and LVCMOS PLL
Clock Synchronizer
Two Reference Clock Inputs (Primary and
Secondary Clock) for Redundancy Support
With Manual or Automatic Selection
Accepts LVCMOS Input Frequencies Up to
200 MHz
VCXO_IN Clock is Synchronized to One of the
Two Reference Clocks
VCXO_IN Frequencies Up to 2 GHz (LVPECL)
Outputs can be a Combination of LVPECL and
LVCMOS (Up to Five Differential LVPECL
Outputs or Up to 10 LVCMOS Outputs)
Output Frequency is Selectable by x1, /2, /3, /4,
/6, /8, /16 on Each Output
Individually
Efficient Jitter Cleaning from Low PLL Loop
Bandwidth
Low Phase Noise PLL Core
Programmable Phase Offset (PRI_REF and
SEC_REF to Outputs)
Wide Charge Pump Current Range From
200 µA to 3 mA
Analog and Digital PLL Lock Indication
Provides VBB Bias Voltage Output for Single-
Ended Input Signals (VCXO_IN)
Frequency Hold Over Mode Improves Fail-Safe
Operation
Power-Up Control Forces LVPECL Outputs to Tri-
State at V_CC < 1.5 V
SPI Controllable Device Setting
3.3-V Power Supply
High-Performance 52 Pin Ceramic Quad Flat
Pack (HFG)
Rad-Tolerant : 50 kRad (Si) TID
QML-V Qualified, SMD 5962-07230
Military Temperature Range: –55°C to 125°C T_case
Engineering Evaluation (/EM) Samples are
Available⁽¹⁾

High Performance LVPECL and LVCMOS PLL
Clock Synchronizer
Two Reference Clock Inputs (Primary and
Secondary Clock) for Redundancy Support
With Manual or Automatic Selection
Accepts LVCMOS Input Frequencies Up to
200 MHz
VCXO_IN Clock is Synchronized to One of the
Two Reference Clocks
VCXO_IN Frequencies Up to 2 GHz (LVPECL)
Outputs can be a Combination of LVPECL and
LVCMOS (Up to Five Differential LVPECL
Outputs or Up to 10 LVCMOS Outputs)
Output Frequency is Selectable by x1, /2, /3, /4,
/6, /8, /16 on Each Output
Individually
Efficient Jitter Cleaning from Low PLL Loop
Bandwidth
Low Phase Noise PLL Core
Programmable Phase Offset (PRI_REF and
SEC_REF to Outputs)
Wide Charge Pump Current Range From
200 µA to 3 mA
Analog and Digital PLL Lock Indication
Provides VBB Bias Voltage Output for Single-
Ended Input Signals (VCXO_IN)
Frequency Hold Over Mode Improves Fail-Safe
Operation
Power-Up Control Forces LVPECL Outputs to Tri-
State at V_CC < 1.5 V
SPI Controllable Device Setting
3.3-V Power Supply
High-Performance 52 Pin Ceramic Quad Flat
Pack (HFG)
Rad-Tolerant : 50 kRad (Si) TID
QML-V Qualified, SMD 5962-07230
Military Temperature Range: –55°C to 125°C T_case
Engineering Evaluation (/EM) Samples are
Available⁽¹⁾

The CDCM7005-SP is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O as VC(X)O_IN / PRI_REF = (N × P) / M or VC(X)O_IN / SEC_REF = (N × P) / M.

VC(X)O_IN clock operates up to 2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.

The CDCM7005-SP can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005-SP are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The LVCMOS outputs are arranged in pairs (Y0A:Y0B, Y1A:Y1B, Ω), so that each pair has the same frequency. But each output can be separately inverted and disabled. The built in synchronization latches ensure that all outputs are synchronized for low output skew.

All device settings, like outputs signaling, divider value, input selection, and many more, are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings.

The device operates in a 3.3-V environment and is characterized for operation from –55°C to 125°C (T_case).

The CDCM7005-SP is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O as VC(X)O_IN / PRI_REF = (N × P) / M or VC(X)O_IN / SEC_REF = (N × P) / M.

VC(X)O_IN clock operates up to 2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.

The CDCM7005-SP can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005-SP are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The LVCMOS outputs are arranged in pairs (Y0A:Y0B, Y1A:Y1B, Ω), so that each pair has the same frequency. But each output can be separately inverted and disabled. The built in synchronization latches ensure that all outputs are synchronized for low output skew.

All device settings, like outputs signaling, divider value, input selection, and many more, are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings.

The device operates in a 3.3-V environment and is characterized for operation from –55°C to 125°C (T_case).

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顶层文档	类型	标题	格式选项	下载最新的英语版本		日期
*	数据表	CDCM7005-SP 3.3-V High Performance Rad-Tolerant Class V, Clock Synchronizer and Jitter Cleaner 数据表 (Rev. G)	PDF \| HTML			2015-12-3
*	辐射与可靠性报告	CDCM7005-SP Single-Event Effects Report				2025-6-4
*	辐射与可靠性报告	CDCM7005MHFG-V Radiation Test Report				2014-11-12
*	SMD	CDCM7005-SP SMD 5962-07230				2016-7-8
	选择指南	TI Space Products (Rev. L)				2026-3-27
	应用简报	经 DLA 批准的 QML 产品优化 (Rev. C)	PDF \| HTML	英语版 (Rev.C)	PDF \| HTML	2025-8-18
	应用手册	重离子轨道环境单粒子效应估算 (Rev. B)	PDF \| HTML	英语版 (Rev.B)	PDF \| HTML	2025-7-7
	更多文献资料	TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B)				2025-2-20
	应用手册	单粒子效应置信区间计算 (Rev. A)	PDF \| HTML	英语版 (Rev.A)	PDF \| HTML	2022-12-2
	电子书	电子产品辐射手册				2022-5-7
	应用手册	Phase Noise/Phase Jitter Performance of CDCM7005				2005-7-26

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CDCM7005EVM-CVAL — CDCM7005-SP 评估模块

CDCM7005 是一款高性能、低相位噪声、低偏差的时钟同步器，可将板载电压控制晶体振荡器 (VC(X)O) 频率与外部参考时钟保持同步。该器件的运行频率高达 2 GHz。PLL 环路带宽和阻尼因数可进行调节以满足不同的系统需求，方法是选择外部 VC(X)O、环路滤波器组件、PFD 的频率以及电荷泵电流。五个差动 LVPECL 和五个 LVCMOS 对输出中的每一个均可通过串行外设接口 (SPI) 进行编程。该 SPI 可以单独控制频率和启用/禁用每个输出的状态。由于系统需要使用外部组件（例如，环路滤波器和 VC(X)O），因此该 EVM (...)

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