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CDCM1804

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1:3 LVPECL 时钟缓冲器 + LVCMOS 输出 + 可编程分频器

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数据表

CDCM1804

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数据表 立即订购

产品详情

Number of outputs 3 Additive RMS jitter (typ) (fs) 150 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Output skew (ps) 30 Operating temperature range (°C) -40 to 85 Rating Catalog Output type 1-LVCMOS No of outputs = 3 LVPECL, LVCMOS, LVPECL Input type LVPECL
Number of outputs 3 Additive RMS jitter (typ) (fs) 150 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Output skew (ps) 30 Operating temperature range (°C) -40 to 85 Rating Catalog Output type 1-LVCMOS No of outputs = 3 LVPECL, LVCMOS, LVPECL Input type LVPECL
VQFN (RGE) 24 16 mm² (4 mm × 4 mm)
  • Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs and One LVCMOS Single-Ended Output
  • Programmable Output Divider for Two LVPECL Outputs and LVCMOS Output
  • Low-Output Skew 15 ps (Typical) for Clock-Distribution Applications for LVPECL Outputs; 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise
  • VCC Range 3 V-3.6 V
  • Signaling Rate Up to 800-MHz LVPECL and 200-MHz LVCMOS
  • Differential Input Stage for Wide Common-Mode Range
  • Provides VBB Bias Voltage Output for Single-Ended Input Signals
  • Receiver Input Threshold ±75 mV
  • 24-Terminal QFN Package (4 mm × 4 mm)
  • Accepts Any Differential Signaling: LVDS, HSTL, CML, VML, SSTL-2, and Single-Ended: LVTTL/LVCMOS
  • Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs and One LVCMOS Single-Ended Output
  • Programmable Output Divider for Two LVPECL Outputs and LVCMOS Output
  • Low-Output Skew 15 ps (Typical) for Clock-Distribution Applications for LVPECL Outputs; 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise
  • VCC Range 3 V-3.6 V
  • Signaling Rate Up to 800-MHz LVPECL and 200-MHz LVCMOS
  • Differential Input Stage for Wide Common-Mode Range
  • Provides VBB Bias Voltage Output for Single-Ended Input Signals
  • Receiver Input Threshold ±75 mV
  • 24-Terminal QFN Package (4 mm × 4 mm)
  • Accepts Any Differential Signaling: LVDS, HSTL, CML, VML, SSTL-2, and Single-Ended: LVTTL/LVCMOS

The CDCM1804 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0], with minimum skew for clock distribution. The CDCM1804 is specifically designed for driving 50- transmission lines. Additionally, the CDCM1804 offers a single-ended LVCMOS output Y3. This output is delayed by 1.6 ns over the three LVPECL output stages to minimize noise impact during signal transitions.

The CDCM1804 has three control terminals, S0, S1, and S2, to select different output mode settings. The S[2:0] terminals are 3-level inputs and therefore allow up to 33 = 27 combinations. Additionally, an enable terminal (EN) is provided to disable or enable all outputs simultaneously. The EN terminal is a 3-level input as well and extends the number of settings to 2 × 27 = 54.

The CDCM1804 is characterized for operation from -40°C to 85°C.

For use in single-ended driver applications, the CDCM1804 also provides a VBB output terminal that can be directly connected to the unused input as a common-mode voltage reference.

The CDCM1804 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0], with minimum skew for clock distribution. The CDCM1804 is specifically designed for driving 50- transmission lines. Additionally, the CDCM1804 offers a single-ended LVCMOS output Y3. This output is delayed by 1.6 ns over the three LVPECL output stages to minimize noise impact during signal transitions.

The CDCM1804 has three control terminals, S0, S1, and S2, to select different output mode settings. The S[2:0] terminals are 3-level inputs and therefore allow up to 33 = 27 combinations. Additionally, an enable terminal (EN) is provided to disable or enable all outputs simultaneously. The EN terminal is a 3-level input as well and extends the number of settings to 2 × 27 = 54.

The CDCM1804 is characterized for operation from -40°C to 85°C.

For use in single-ended driver applications, the CDCM1804 also provides a VBB output terminal that can be directly connected to the unused input as a common-mode voltage reference.
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技术文档

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 1:3 LVPECL Clock Buffer & Addl LVCMOS Output & Programmable Divider 数据表 (Rev. E) 2005-5-22
应用手册 CDCM1802/CDCM1804 2004-8-4

设计与开发

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仿真模型

CDCM1804 IBIS Model

SCAC047.ZIP (24 KB) - IBIS 模型
支持的产品和硬件
封装 引脚 CAD 符号、封装和 3D 模型
VQFN (RGE) 24 Ultra Librarian
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