CDCLVP111
- Distributes One Differential Clock Input Pair
LVPECL to 10 Differential LVPECL - Fully Compatible With LVECL and LVPECL
- Supports a Wide Supply Voltage Range from
2.375 V to 3.8 V - Selectable Clock Input Through CLK_SEL
- Low-Output Skew (Typical 15 ps) for Clock-
Distribution Applications- Additive Jitter Less Than 1 ps
- Propagation Delay Less Than 350 ps
- Open Input Default State
- LVDS, CML, SSTL Input Compatible
- VBB Reference Voltage Output for Single-Ended
Clocking - Available in a 32-Pin LQFP and QFN Package
- Frequency Range From DC to 3.5 GHz
- Pin-to-Pin Compatible With MC100 Series EP111,
ES6111, LVEP111, PTN1111 - APPLICATIONS
- Designed for Driving 50-Ω Transmission Lines
- High Performance Clock Distribution
All other trademarks are the property of their respective owners
The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111 can accept two clock sources into an input multiplexer. The CDCLVP111 is specifically designed for driving 50-Ω transmission lines. When an output pin is not used, leaving it open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50 Ω.
The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin should be connected to CLK0 and bypassed to GND through a 10-nF capacitor.
However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.
The CDCLVP111 device is characterized for operation from –40°C to 85°C.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | CDCLVP111 Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver 数据表 (Rev. F) | PDF | HTML | 2015-6-30 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
CLOCK-TREE-ARCHITECT — 时钟树架构编程软件
时钟树架构是一款时钟树综合工具，可根据您的系统要求生成时钟树解决方案，从而帮助您简化设计流程。该工具从庞大的时钟产品数据库中提取数据，然后生成系统级多芯片时钟解决方案。
PLLATINUMSIM-SW — PLL 环路滤波器、相位噪声、锁定时间和杂散模拟工具
PLLATINUMSIM-SW 是一款仿真工具，允许用户创建我们 PLLatinum™ 集成电路的详细设计和仿真，其中包括 LMX 系列锁相环 (PLL) 和合成器。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VQFN (RHB) | 32 | Ultra Librarian |
| LQFP (VF) | 32 | Ultra Librarian |
订购和质量
推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。