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CDCE906

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167MHz、LVCMOS、可编程 3-PLL 时钟合成器/倍频器/分频器

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CDCE906

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产品详情

Number of outputs 6 Output type LVCMOS Output frequency (max) (MHz) 167 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type Differential, LVCMOS, XTAL Operating temperature range (°C) 0 to 70 Features I2C, Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Catalog
Number of outputs 6 Output type LVCMOS Output frequency (max) (MHz) 167 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type Differential, LVCMOS, XTAL Operating temperature range (°C) 0 to 70 Features I2C, Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Catalog
TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm)
  • High Performance 3:6 PLL based Clock Synthesizer / Multiplier / Divider
  • User Programmable PLL Frequencies
  • EEPROM Programming Without the Need to Apply High Programming Voltage
  • Easy In-Circuit Programming via SMBus Data Interface
  • Wide PLL Divider Ratio Allows 0-ppm Output Clock Error
  • Generates Precise Video (27 MHz or 54 MHz) and Audio System Clocks from Multiple Sampling Frequencies (fS = 16, 22.05, 24, 32, 44.1, 48, 96 kHz)
  • Clock Inputs Accept a Crystal or a Single-Ended LVCMOS or a Differential Input Signal
  • Accepts Crystal Frequencies from 8 MHz up to 54 MHz
  • Accepts LVCMOS or Differential Input Frequencies up to 167 MHz
  • Two Programmable Control Inputs [S0/S1, A0/A1] for User Defined Control Signals
  • Six LVCMOS Outputs with Output Frequencies up to 167 MHz
  • LVCMOS Outputs can be Programmed for Complementary Signals
  • Free Selectable Output Frequency via Programmable Output Switching Matrix [6x6] Including 7-Bit Post-Divider for Each Output
  • PLL Loop Filter Components Integrated
  • Low Period Jitter (Typ 60 ps)
  • Features Spread Spectrum Clocking (SSC) for Lowering System EMI
  • Programmable Center Spread SSC Modulation (±0.1%, ±0.25%, and ±0.4%) with a Mean Phase Equal to the Phase of the Non-Modulated Frequency
  • Programmable Down Spread SSC Modulation (1%, 1.5%, 2%, and 3%)
  • Programmable Output Slew-Rate Control (SRC) for Lowering System EMI
  • 3.3-V Device Power Supply
  • Commercial Temperature Range 0°C to 70°C
  • Development and Programming Kit for Easy PLL Design and Programming
    (TI Pro-Clock™)
  • Packaged in 20-Pin TSSOP

Pro-Clock is a trademark of Texas Instruments.
  • High Performance 3:6 PLL based Clock Synthesizer / Multiplier / Divider
  • User Programmable PLL Frequencies
  • EEPROM Programming Without the Need to Apply High Programming Voltage
  • Easy In-Circuit Programming via SMBus Data Interface
  • Wide PLL Divider Ratio Allows 0-ppm Output Clock Error
  • Generates Precise Video (27 MHz or 54 MHz) and Audio System Clocks from Multiple Sampling Frequencies (fS = 16, 22.05, 24, 32, 44.1, 48, 96 kHz)
  • Clock Inputs Accept a Crystal or a Single-Ended LVCMOS or a Differential Input Signal
  • Accepts Crystal Frequencies from 8 MHz up to 54 MHz
  • Accepts LVCMOS or Differential Input Frequencies up to 167 MHz
  • Two Programmable Control Inputs [S0/S1, A0/A1] for User Defined Control Signals
  • Six LVCMOS Outputs with Output Frequencies up to 167 MHz
  • LVCMOS Outputs can be Programmed for Complementary Signals
  • Free Selectable Output Frequency via Programmable Output Switching Matrix [6x6] Including 7-Bit Post-Divider for Each Output
  • PLL Loop Filter Components Integrated
  • Low Period Jitter (Typ 60 ps)
  • Features Spread Spectrum Clocking (SSC) for Lowering System EMI
  • Programmable Center Spread SSC Modulation (±0.1%, ±0.25%, and ±0.4%) with a Mean Phase Equal to the Phase of the Non-Modulated Frequency
  • Programmable Down Spread SSC Modulation (1%, 1.5%, 2%, and 3%)
  • Programmable Output Slew-Rate Control (SRC) for Lowering System EMI
  • 3.3-V Device Power Supply
  • Commercial Temperature Range 0°C to 70°C
  • Development and Programming Kit for Easy PLL Design and Programming
    (TI Pro-Clock™)
  • Packaged in 20-Pin TSSOP

Pro-Clock is a trademark of Texas Instruments.

The CDCE906 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite its small physical outlines, the CDCE906 is flexible. It has the capability to produce an almost independent output frequency from a given input frequency.

The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller.

To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output.

The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (e.g., a 27 MHz).

The CDCE906 includes three PLLs of those one supports SSC (spread-spectrum clocking). PLL1, PLL2, and PLL3 are designed for frequencies up to 167 MHz and optimized for zero-ppm applications with wide divider factors.

PLL2 also supports center-spread and down-spread spectrum clocking (SSC). This is a common technique to reduce electro-magnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.

Based on the PLL frequency and the divider settings, the internal loop filter components will be automatically adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL.

The device supports non-volatile EEPROM programming for easy-customized application. It is preprogrammed with a factory default configuration (see Figure 13) and can be reprogrammed to a different application configuration before it goes onto the PCB or reprogrammed by in-system programming. A different device setting is programmed via the serial SMBus interface.

Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding logic control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).

The CDCE906 has three power supply pins, VCC, VCCOUT1 and VCCOUT2. VCC is the power supply for the device. It operates from a single 3.3-V supply voltage. VCCOUT1 and VCCOUT2 are the power supply pins for the outputs. VCCOUT1 supplies the outputs Y0 and Y1 and VCCOUT2 supplies the outputs Y2, Y3, Y4, and Y5. Both outputs supplies can be 2.3 V to 3.6 V. At output voltages lower than 3.3 V, the output drive current is limited.

The CDCE906 is characterized for operation from 0°C to 70°C.

The CDCE906 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite its small physical outlines, the CDCE906 is flexible. It has the capability to produce an almost independent output frequency from a given input frequency.

The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller.

To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output.

The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (e.g., a 27 MHz).

The CDCE906 includes three PLLs of those one supports SSC (spread-spectrum clocking). PLL1, PLL2, and PLL3 are designed for frequencies up to 167 MHz and optimized for zero-ppm applications with wide divider factors.

PLL2 also supports center-spread and down-spread spectrum clocking (SSC). This is a common technique to reduce electro-magnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.

Based on the PLL frequency and the divider settings, the internal loop filter components will be automatically adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL.

The device supports non-volatile EEPROM programming for easy-customized application. It is preprogrammed with a factory default configuration (see Figure 13) and can be reprogrammed to a different application configuration before it goes onto the PCB or reprogrammed by in-system programming. A different device setting is programmed via the serial SMBus interface.

Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding logic control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).

The CDCE906 has three power supply pins, VCC, VCCOUT1 and VCCOUT2. VCC is the power supply for the device. It operates from a single 3.3-V supply voltage. VCCOUT1 and VCCOUT2 are the power supply pins for the outputs. VCCOUT1 supplies the outputs Y0 and Y1 and VCCOUT2 supplies the outputs Y2, Y3, Y4, and Y5. Both outputs supplies can be 2.3 V to 3.6 V. At output voltages lower than 3.3 V, the output drive current is limited.

The CDCE906 is characterized for operation from 0°C to 70°C.
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 Programmable 3-PLL Clock Synthesizer / Multiplier/Divider 数据表 (Rev. H) 2007-12-11
应用手册 High Speed Layout Guidelines (Rev. A) 2017-8-8
用户指南 CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual (Rev. A) 2010-11-22
应用手册 Troubleshooting I2C Bus Protocol 2009-10-19
应用手册 CDCx706/x906 Termination and Signal Integrity Guidelines (Rev. A) 2007-11-28
用户指南 CDCE906/CDCE706 Performance EVM (Rev. B) 2007-4-17
应用手册 Clock Recommendations for the DM643x EVM 2006-11-29
应用手册 Recommended Terminations for the Differential Inputs of CDCE906/CDCE706 2006-8-10

设计与开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

评估板

CDCE906-706PERFEVM — CDCE906 和 CDCE706 评估模块

CDCE906-706PERF 评估模块可验证具有晶振差分输入和 LVCMOS 输入选项的 CDCE906 和 CDCE706 的功能和性能。可以通过 SMA 电缆将六个输出直接连接到示波器。
支持的产品和硬件
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限制：
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无货
评估板

CDCE906-706PROGEVM — CDCE906 和 CDCE706 可编程 EVM

用户指南: PDF
支持的产品和硬件
有库存
限制：
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无货
应用软件和框架

SCAC097 — Executable File Without LabVIEW 8.2 Run Time Engine

支持的产品和硬件
支持软件

CLOCKPRO — ClockPro Software

TI's ClockPro software allows users to program/configure the following devices in a friendly GUI interface:

  • CDCE949
  • CDCE937
  • CDCE925
  • CDCE913
  • CDCE906
  • CDCE706
  • CDCEL949
  • CDCEL937
  • CDCEL925
  • CDCEL913

It is intended to be used with the evaluation modules of the above devices.

支持的产品和硬件
支持软件

SCAC073 — TI-Pro-Clock Programming Software

支持的产品和硬件
仿真模型

CDCE906 IBIS Model (Rev. A)

SCAC071 (646 KB) - IBIS 模型
支持的产品和硬件
参考设计

TIDA-00080 — 基于隔离式 Δ-Σ 调制器的交流/直流电压和电流测量模块参考设计

这是一种基于并联的隔离式电流测量装置，无需使用电流互感器 (CT) 即可实现高精度电流测量。隔离是通过使用集成了高压隔离以及 Δ-Σ 调制器的 AMC1304 实现的。此解决方案消除了对客户重视的 CT 的需求，因为 CT 的电路板尺寸减小，产品重量减轻，缓解系统中的串扰和 EMI，并且可以通过用分流器替换 CT 来减少机械问题，从而延长产品寿命。

支持的产品和硬件
参考设计

TIDA-00171 — 适用于电机驱动器的隔离式电流分流和电压测量参考设计

此评估套件和参考设计在 C2000™ TMS320F28377D Delfino™ 微控制器中实现了 AMC130x 增强型隔离式 Δ-Σ 调制器以及集成式 Sinc 滤波器。此设计能够评估这些测量值的性能：三个电机电流、三个逆变器电压以及直流链路电压。  套件中提供了固件来配置 Sinc 滤波器、设置 PLL 频率以及接收 Sinc 滤波器的数据。还提供多功能运行时 GUI 来帮助用户验证 AMC130x 性能，并支持对 Delfino 控制器中的 Sinc 滤波器参数进行配置更改。

支持的产品和硬件
封装 引脚 CAD 符号、封装和 3D 模型
TSSOP (PW) 20 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

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