CDCE706

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300MHz、LVCMOS、可编程 3-PLL 时钟合成器/倍频器/分频器

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数据表

document-pdfAcrobat Programmable 3-PLL Clock Synthesizer / Multiplier / Divider 数据表 (Rev. I) (英语)

CDCE706

正在供货

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产品详情

Number of outputs

6

Output type

LVCMOS

Output frequency (max) (MHz)

300

Core supply voltage (V)

3.3

Output supply voltage (V)

3.3

Input type

Differential, LVCMOS, XTAL

Operating temperature range (°C)

-40 to 85

Features

Integrated EEPROM, Pin programmable, SMBus, Spread-spectrum clocking (SSC)

Rating

Catalog

Number of outputs

6

Output type

LVCMOS

Output frequency (max) (MHz)

300

Core supply voltage (V)

3.3

Output supply voltage (V)

3.3

Input type

Differential, LVCMOS, XTAL

Operating temperature range (°C)

-40 to 85

Features

Integrated EEPROM, Pin programmable, SMBus, Spread-spectrum clocking (SSC)

Rating

Catalog

TSSOP (PW)

20

41.6 mm² (6.5 mm × 6.4 mm)

High Performance 3:6 PLL Based Clock Synthesizer / Multiplier / Divider
User Programmable PLL Frequencies
EEPROM Programming Without the Need to Apply High Programming Voltage
Easy In-Circuit Programming via SMBus Data Interface
Wide PLL Divider Ratio Allows 0-ppm Output Clock Error
Clock Inputs Accept a Crystal or a Single-Ended LVCMOS or a Differential Input Signal
Accepts Crystal Frequencies from 8 MHz up to 54 MHz
Accepts LVCMOS or Differential Input Frequencies up to 200 MHz
Two Programmable Control Inputs [S0/S1, A0/A1] for User Defined Control Signals
Six LVCMOS Outputs with Output Frequencies up to 300 MHz
LVCMOS Outputs can be Programmed for Complementary Signals
Free Selectable Output Frequency via Programmable Output Switching Matrix [6x6] Including 7-Bit Post-Divider for Each Output
PLL Loop Filter Components Integrated
Low Period Jitter (Typ 60 ps)
Features Spread Spectrum Clocking (SSC) for Lowering System EMI
Programmable Output Slew-Rate Control (SRC) for Lowering System EMI
3.3-V Device Power Supply
Industrial Temperature Range -40°C to 85°C
Development and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock™)
Packaged in 20-Pin TSSOP

High Performance 3:6 PLL Based Clock Synthesizer / Multiplier / Divider
User Programmable PLL Frequencies
EEPROM Programming Without the Need to Apply High Programming Voltage
Easy In-Circuit Programming via SMBus Data Interface
Wide PLL Divider Ratio Allows 0-ppm Output Clock Error
Clock Inputs Accept a Crystal or a Single-Ended LVCMOS or a Differential Input Signal
Accepts Crystal Frequencies from 8 MHz up to 54 MHz
Accepts LVCMOS or Differential Input Frequencies up to 200 MHz
Two Programmable Control Inputs [S0/S1, A0/A1] for User Defined Control Signals
Six LVCMOS Outputs with Output Frequencies up to 300 MHz
LVCMOS Outputs can be Programmed for Complementary Signals
Free Selectable Output Frequency via Programmable Output Switching Matrix [6x6] Including 7-Bit Post-Divider for Each Output
PLL Loop Filter Components Integrated
Low Period Jitter (Typ 60 ps)
Features Spread Spectrum Clocking (SSC) for Lowering System EMI
Programmable Output Slew-Rate Control (SRC) for Lowering System EMI
3.3-V Device Power Supply
Industrial Temperature Range -40°C to 85°C
Development and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock™)
Packaged in 20-Pin TSSOP

The CDCE706 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite its small physical outlines, the CDCE706 is very flexible. It has the capability to produce an almost independent output frequency from a given input frequency.

The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller.

To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output.

The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (e.g., a 27-MHz).

The CDCE706 includes three PLLs of those one supports SSC (spread-spectrum clocking). PLL1, PLL2, and PLL3 are designed for frequencies up to 300 MHz and optimized for zero-ppm applications with wide divider factors.

PLL2 also supports center-spread and down-spread spectrum clocking (SSC). This is a common technique to reduce electro-magnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.

Based on the PLL frequency and the divider settings, the internal loop filter components will be automatically adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL.

The device supports non-volatile EEPROM programming for easy-customized application. It is preprogrammed with a factory default configuration (see Figure 13) and can be reprogrammed to a different application configuration before it goes onto the PCB or re-programmed by in-system programming. A different device setting is programmed via the serial SMBus Interface.

Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding logic control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).

The CDCE706 has three power supply pins, V_CC, V_CCOUT1, and V_CCOUT2. V_CC is the power supply for the device. It operates from a single 3.3-V supply voltage. V_CCOUT1 and V_CCOUT2 are the power supply pins for the outputs. V_CCOUT1 supplies the outputs Y0 and Y1 and V_CCOUT2 supplies the outputs Y2, Y3, Y4, and Y5. Both outputs supplies can be 2.3 V to 3.6 V. At output voltages lower than 3.3 V, the output drive current is limited.

The CDCE706 is characterized for operation from -40°C to 85°C.