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CDC341

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通过输出控制引脚实现低电平状态的 1:8 TTL 时钟驱动器

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CDC341

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Number of outputs 8 Core supply voltage (V) 5 Output supply voltage (V) 5 Output skew (ps) 0.6 Operating temperature range (°C) 0 to 70 Rating Catalog Output type TTL Input type TTL
Number of outputs 8 Core supply voltage (V) 5 Output supply voltage (V) 5 Output skew (ps) 0.6 Operating temperature range (°C) 0 to 70 Rating Catalog Output type TTL Input type TTL
SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm)
  • Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
  • TTL-Compatible Inputs and Outputs
  • Distributes One Clock Input to Eight Outputs
  • Distributed VCC and Ground Pins Reduce Switching Noise
  • High-Drive Outputs (-48-mA IOH, 48-mA IOL)
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Packaging Options Include Plastic Small-Outline (DW) Packages

    EPIC-IIB is a trademark of Texas Instruments Incorporated.
  • Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
  • TTL-Compatible Inputs and Outputs
  • Distributes One Clock Input to Eight Outputs
  • Distributed VCC and Ground Pins Reduce Switching Noise
  • High-Drive Outputs (-48-mA IOH, 48-mA IOL)
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Packaging Options Include Plastic Small-Outline (DW) Packages

    EPIC-IIB is a trademark of Texas Instruments Incorporated.

The CDC341 is a high-performance clock-driver circuit that distributes one (A) input signal to eight (Y) outputs with minimum skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be placed in a low state regardless of the A input.

The propagation delays are adjusted at the factory using the P0 and P1 pins. These pins are not intended for customer use and should be strapped to GND.

The CDC341 is characterized for operation from 0°C to 70°C.

The CDC341 is a high-performance clock-driver circuit that distributes one (A) input signal to eight (Y) outputs with minimum skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be placed in a low state regardless of the A input.

The propagation delays are adjusted at the factory using the P0 and P1 pins. These pins are not intended for customer use and should be strapped to GND.

The CDC341 is characterized for operation from 0°C to 70°C.

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* 数据表 1-Line To 8-Line Clock Driver 数据表 (Rev. D) 1998-10-27

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SOIC (DW) 20 Ultra Librarian
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