CD40109B
- Independence of power supply sequence considerations - VCC can exceed VDD, input signals can exceed both VCC and VDD
- Up and down level-shifting capability
- Three-state outputs with separate enable controls
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range):
= 1 V at VCC = 5 V, VDD = 10 V
= 2 V at VCC = 10 V, VDD = 15 V - 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Applications:
- High-or-low level-shifting with three-state outputs for unidirectional or bidirectional bussing.
- Isolation of logic subsystems using separate power supplies from supply sequencing, supply loss and supply regulation considerations
Data sheet acquired from Harris Semiconductor
CD40109B contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic input signal (A, B, C, D) with logical 1 = VCC and logical 0 = VSS to a higher-voltage output signal (E, F, G, H) with logical 1 = VDD and logical 0 = VSS.
The CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSS and at least 0.7 VCC; VCC may exceed VDD, and input signals may exceed VCC and VDD. When operated in the mode VCC > VDD, the CD40109 will operate as a high-to-low level-shifter.
The CD40109 also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output.
The CD40109B-Series types are supplied in 16-lead ceramic dual-in-line packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
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技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | CD40109B TYPES 数据表 (Rev. B) | 2003-1-15 | |||
| 应用手册 | 原理图检查清单 - 使用自动双向转换器进行设计的指南 | PDF | HTML | 英语版 | PDF | HTML | 2024-12-3 | |
| 应用手册 | 原理图检查清单 - 使用固定或方向控制转换器进行设计的指南 | PDF | HTML | 英语版 | PDF | HTML | 2024-10-3 | |
| 应用手册 | Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) | PDF | HTML | 2024-7-3 | |||
| 应用简报 | 利用 TXH 实现高电压电平转换 | PDF | HTML | 英语版 | PDF | HTML | 2023-10-6 | |
| 选择指南 | Voltage Translation Buying Guide (Rev. A) | 2021-4-15 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块
14-24-LOGIC-EVM 评估模块 (EVM) 设计用于支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| SOP (NS) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
| PDIP (N) | 16 | Ultra Librarian |