ADS62P28
- Maximum Sample Rate: 250 MSPS
- 14-Bit Resolution – ADS62P49/ADS62P48
- 12-Bit Resolution – ADS62P29/ADS62P28
- Total Power: 1.25 W at 250 MSPS
- Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
- Programmable Gain up to 6dB for SNR/SFDR Trade-Off
- DC Offset Correction
- 90dB Cross-Talk
- Supports Input Clock Amplitude Down to 400 mVPP Differential
- Internal and External Reference Support
- 64-QFN Package (9 mm × 9 mm)
The ADS62Px9/x8 is a family of dual channel 14-bit and 12-bit A/D converters with sampling rates up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 64 QFN package. This makes it well-suited for multi-carrier, wide band-width communications applications.
The ADS62Px9/x8 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available.
It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | Dual Channel 14-/12-Bit, 250/210 MSPS ADC with DDR LVDS & Parallel CMOS Outputs 数据表 (Rev. B) | 2011-1-4 | |||
| * | 用户指南 | Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) | 2012-7-10 | |||
| 应用手册 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015-5-22 | ||||
| 应用手册 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013-7-19 | ||||
| 用户指南 | TSW4200 Demonstration Kit User's Guide (Rev. C) | 2012-10-31 | ||||
| 应用手册 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010-9-10 | ||||
| 应用手册 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009-4-28 | ||||
| 应用手册 | CDCE62005 as Clock Solution for High-Speed ADCs | 2008-9-4 | ||||
| 应用手册 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008-6-8 | ||||
| 应用手册 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008-6-2 | ||||
| 应用手册 | QFN Layout Guidelines | 2006-7-28 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
DATACONVERTERPRO-SW — 高速数据转换器专业 GUI 安装程序，v5.31
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| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VQFN (RGC) | 64 | Ultra Librarian |