ADS6142

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14 位、65MSPS 模数转换器 (ADC)

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数据表

document-pdfAcrobat 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS 数据表 (Rev. B) (英语)

ADS6142

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产品详情

Sample rate (max) (Msps)

65

Resolution (Bits)

14

Number of input channels

1

Interface type

DDR LVDS, Parallel CMOS

Analog input BW (MHz)

500

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

285

Architecture

Pipeline

SNR (dB)

74.7

ENOB (Bits)

12

SFDR (dB)

95

Operating temperature range (°C)

-40 to 85

Input buffer

No

Sample rate (max) (Msps)

65

Resolution (Bits)

14

Number of input channels

1

Interface type

DDR LVDS, Parallel CMOS

Analog input BW (MHz)

500

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

285

Architecture

Pipeline

SNR (dB)

74.7

ENOB (Bits)

12

SFDR (dB)

95

Operating temperature range (°C)

-40 to 85

Input buffer

No

VQFN (RHB)

32

25 mm² (5 mm × 5 mm)

Maximum Sample Rate: 125 MSPS
14-Bit Resolution with No Missing Codes
3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-Off
Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs, and Clock Amplitude Down to 400 mV_PP
Clock Duty Cycle Stabilizer
Internal Reference with Support for External Reference
No External Decoupling Required for References
Programmable Output Clock Position and Drive Strength to Ease Data Capture
3.3-V Analog and 1.8-V to 3.3-V Digital Supply
32-QFN Package (5 mm × 5 mm)
Pin Compatible 12-Bit Family (ADS612X)
APPLICATIONS
- Wireless Communications Infrastructure
- Software Defined Radio
- Power Amplifier Linearization
- 802.16d/e
- Test and Measurement Instrumentation
- High Definition Video
- Medical Imaging
- Radar Systems

Maximum Sample Rate: 125 MSPS
14-Bit Resolution with No Missing Codes
3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-Off
Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs, and Clock Amplitude Down to 400 mV_PP
Clock Duty Cycle Stabilizer
Internal Reference with Support for External Reference
No External Decoupling Required for References
Programmable Output Clock Position and Drive Strength to Ease Data Capture
3.3-V Analog and 1.8-V to 3.3-V Digital Supply
32-QFN Package (5 mm × 5 mm)
Pin Compatible 12-Bit Family (ADS612X)
APPLICATIONS
- Wireless Communications Infrastructure
- Software Defined Radio
- Power Amplifier Linearization
- 802.16d/e
- Test and Measurement Instrumentation
- High Definition Video
- Medical Imaging
- Radar Systems

ADS6145/ADS6144/ADS6143/ADS6142 (ADS614X) are a family of 14-bit A/D converters with sampling frequencies up to 125 MSPS. The high performance and low power consumption of the ADS614X are combined in a compact 32 QFN package. An internal high bandwidth sample and hold and a low jitter clock buffer help to achieve high SNR and high SFDR even at high input frequencies.

The ADS614X feature coarse and fine gain options to improve SFDR performance at lower full-scale analog input ranges.

The digital data outputs are either parallel CMOS or DDR (Double Data Rate) LVDS. Several features exist to ease data capture such as — controls for output clock position and output buffer drive strength, LVDS current, and internal termination programmability.

The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some functions are configured using dedicated parallel pins so the device powers up to the desired state.

The ADS614X include internal references while eliminating traditional reference pins and associated external decoupling. External reference mode is also supported.

The ADS614X are specified over the industrial temperature range (-40°C to 85°C).

ADS6145/ADS6144/ADS6143/ADS6142 (ADS614X) are a family of 14-bit A/D converters with sampling frequencies up to 125 MSPS. The high performance and low power consumption of the ADS614X are combined in a compact 32 QFN package. An internal high bandwidth sample and hold and a low jitter clock buffer help to achieve high SNR and high SFDR even at high input frequencies.

The ADS614X feature coarse and fine gain options to improve SFDR performance at lower full-scale analog input ranges.

The digital data outputs are either parallel CMOS or DDR (Double Data Rate) LVDS. Several features exist to ease data capture such as — controls for output clock position and output buffer drive strength, LVDS current, and internal termination programmability.

The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some functions are configured using dedicated parallel pins so the device powers up to the desired state.

The ADS614X include internal references while eliminating traditional reference pins and associated external decoupling. External reference mode is also supported.

The ADS614X are specified over the industrial temperature range (-40°C to 85°C).

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ADS4142

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技术文档

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顶层文档	类型	标题	日期
*	数据表	14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS 数据表 (Rev. B)	2007-12-4
	应用手册	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)	2015-5-22
	应用手册	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)	2013-7-19
	应用手册	Band-Pass Filter Design Techniques for High-Speed ADCs	2012-2-27
	应用手册	Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)	2010-9-10
	应用手册	Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio	2009-4-28
	应用手册	CDCE62005 as Clock Solution for High-Speed ADCs	2008-9-4
	应用手册	CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters	2008-6-8
	应用手册	Phase Noise Performance and Jitter Cleaning Ability of CDCE72010	2008-6-2
	应用手册	QFN Layout Guidelines	2006-7-28

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