ADS6129

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12 位、250MSPS 模数转换器 (ADC)

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数据表

document-pdfAcrobat 14/12 Bit, 250/210 MSPS ADC with DDR LVDS and Parallel CMOS Outputs 数据表 (Rev. B) (英语)

ADS6129

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产品详情

Sample rate (max) (Msps)

250

Resolution (Bits)

12

Number of input channels

1

Interface type

Parallel CMOS, Parallel LVDS

Analog input BW (MHz)

700

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

687

Architecture

Pipeline

SNR (dB)

70.7

ENOB (Bits)

11.2

SFDR (dB)

92

Operating temperature range (°C)

-40 to 85

Input buffer

No

Sample rate (max) (Msps)

250

Resolution (Bits)

12

Number of input channels

1

Interface type

Parallel CMOS, Parallel LVDS

Analog input BW (MHz)

700

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

687

Architecture

Pipeline

SNR (dB)

70.7

ENOB (Bits)

11.2

SFDR (dB)

92

Operating temperature range (°C)

-40 to 85

Input buffer

No

VQFN (RGZ)

48

49 mm² (7 mm × 7 mm)

Maximum Sample Rate: 250 MSPS
14-Bit Resolution — ADS614X
12-Bit Resolution — ADS612X
687 mW Total Power Dissipation at 250 MSPS
Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
Programmable Fine Gain up to 6dB for SNR/SFDR Trade-Off
DC Offset Correction
Supports Input Clock Amplitude Down to 400 mV_PP Differential
Internal and External Reference Support
48-QFN Package (7mm × 7mm)
Pin Compatible with ADS5547 Family
APPLICATIONS
- Multicarrier, Wide Band-Width Communications
- Wireless Multi-carrier Communications Infrastructure
- Software Defined Radio
- Power Amplifier Linearization
- 802.16d/e
- Test and Measurement Instrumentation
- High Definition Video
- Medical Imaging
- Radar Systems

Maximum Sample Rate: 250 MSPS
14-Bit Resolution — ADS614X
12-Bit Resolution — ADS612X
687 mW Total Power Dissipation at 250 MSPS
Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
Programmable Fine Gain up to 6dB for SNR/SFDR Trade-Off
DC Offset Correction
Supports Input Clock Amplitude Down to 400 mV_PP Differential
Internal and External Reference Support
48-QFN Package (7mm × 7mm)
Pin Compatible with ADS5547 Family
APPLICATIONS
- Multicarrier, Wide Band-Width Communications
- Wireless Multi-carrier Communications Infrastructure
- Software Defined Radio
- Power Amplifier Linearization
- 802.16d/e
- Test and Measurement Instrumentation
- High Definition Video
- Medical Imaging
- Radar Systems

ADS614X (ADS612X) is a family of 14-bit (12-bit) A/D converters with sampling rates up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 48 QFN package. This makes it well-suited for multicarrier, wide band-width communications applications.

ADS614X/2X has fine gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.

It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (-40°C to 85°C).

ADS614X (ADS612X) is a family of 14-bit (12-bit) A/D converters with sampling rates up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 48 QFN package. This makes it well-suited for multicarrier, wide band-width communications applications.

ADS614X/2X has fine gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.

It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (-40°C to 85°C).

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顶层文档	类型	标题	日期
*	数据表	14/12 Bit, 250/210 MSPS ADC with DDR LVDS and Parallel CMOS Outputs 数据表 (Rev. B)	2008-10-10
	应用手册	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)	2015-5-22
	应用手册	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)	2013-7-19
	应用手册	Band-Pass Filter Design Techniques for High-Speed ADCs	2012-2-27
	应用手册	Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)	2010-9-10
	应用手册	Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio	2009-4-28
	应用手册	CDCE62005 as Clock Solution for High-Speed ADCs	2008-9-4
	应用手册	CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters	2008-6-8
	应用手册	Phase Noise Performance and Jitter Cleaning Ability of CDCE72010	2008-6-2
	应用手册	QFN Layout Guidelines	2006-7-28

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