ADS6124

正在供货

12 位、105MSPS 模数转换器 (ADC)

立即订购

数据表

document-pdfAcrobat 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS and CMOS OUTPUTS 数据表 (Rev. A) (英语)

ADS6124

正在供货

立即订购

产品详情

Sample rate (max) (Msps)

105

Resolution (Bits)

12

Number of input channels

1

Interface type

DDR LVDS, Parallel CMOS

Analog input BW (MHz)

500

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

374

Architecture

Pipeline

SNR (dB)

71.5

ENOB (Bits)

11.5

SFDR (dB)

91

Operating temperature range (°C)

-40 to 85

Input buffer

No

Sample rate (max) (Msps)

105

Resolution (Bits)

12

Number of input channels

1

Interface type

DDR LVDS, Parallel CMOS

Analog input BW (MHz)

500

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

374

Architecture

Pipeline

SNR (dB)

71.5

ENOB (Bits)

11.5

SFDR (dB)

91

Operating temperature range (°C)

-40 to 85

Input buffer

No

VQFN (RHB)

32

25 mm² (5 mm × 5 mm)

Maximum Sample Rate: 125 MSPS
12-Bit Resolution with No Missing Codes
3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-Off
Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mV_PP
Clock Duty Cycle Stabilizer
Internal Reference with Support for External Reference
No External Decoupling Required for References
Programmable Output Clock Position and Drive Strength to Ease Data Capture
3.3 V Analog and 1.8 V to 3.3 V Digital Supply
32-QFN Package (5 mm × 5 mm)
Pin Compatible 12-Bit Family (ADS612X)
APPLICATIONS
- Wireless Communications Infrastructure
- Software Defined Radio
- Power Amplifier Linearization
- 802.16d/e
- Test and Measurement Instrumentation
- High Definition Video
- Medical Imaging
- Radar Systems

Maximum Sample Rate: 125 MSPS
12-Bit Resolution with No Missing Codes
3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-Off
Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mV_PP
Clock Duty Cycle Stabilizer
Internal Reference with Support for External Reference
No External Decoupling Required for References
Programmable Output Clock Position and Drive Strength to Ease Data Capture
3.3 V Analog and 1.8 V to 3.3 V Digital Supply
32-QFN Package (5 mm × 5 mm)
Pin Compatible 12-Bit Family (ADS612X)
APPLICATIONS
- Wireless Communications Infrastructure
- Software Defined Radio
- Power Amplifier Linearization
- 802.16d/e
- Test and Measurement Instrumentation
- High Definition Video
- Medical Imaging
- Radar Systems

ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X) is a family of 12-bit A/D converters with sampling frequencies up to 125 MSPS. It combines high performance and low power consumption in a compact 32 QFN package. Using an internal high bandwidth sample and hold and a low jitter clock buffer helps to achieve high SNR and high SFDR even at high input frequencies.

It features coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges.

The digital data outputs are either parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture such as — controls for output clock position and output buffer drive strength, and LVDS current and internal termination programmability.

The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured using dedicated parallel pins so that the device comes up in the desired state after power-up.

ADS612X includes internal references, while eliminating the traditional reference pins and associated external decoupling. External reference mode is also supported.

The devices are specified over the industrial temperature range (-40°C to 85°C).

ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X) is a family of 12-bit A/D converters with sampling frequencies up to 125 MSPS. It combines high performance and low power consumption in a compact 32 QFN package. Using an internal high bandwidth sample and hold and a low jitter clock buffer helps to achieve high SNR and high SFDR even at high input frequencies.

It features coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges.

The digital data outputs are either parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture such as — controls for output clock position and output buffer drive strength, and LVDS current and internal termination programmability.

The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured using dedicated parallel pins so that the device comes up in the desired state after power-up.

ADS612X includes internal references, while eliminating the traditional reference pins and associated external decoupling. External reference mode is also supported.

The devices are specified over the industrial temperature range (-40°C to 85°C).

filter

查找其他高速 ADC (≥10 MSPS)

下载观看带字幕的视频视频

您可能感兴趣的相似产品

open-in-new

比较替代产品

功能与比较器件相同且具有相同引脚。

ADS6144

正在供货

14 位、105MSPS 模数转换器 (ADC) Pin-for-pin 14-bit upgrade

技术文档

未找到结果。请清除搜索并重试。

查看全部 10

顶层文档	类型	标题	日期
*	数据表	12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS and CMOS OUTPUTS 数据表 (Rev. A)	2007-12-4
	应用手册	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)	2015-5-22
	应用手册	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)	2013-7-19
	应用手册	Band-Pass Filter Design Techniques for High-Speed ADCs	2012-2-27
	应用手册	Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)	2010-9-10
	应用手册	Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio	2009-4-28
	应用手册	CDCE62005 as Clock Solution for High-Speed ADCs	2008-9-4
	应用手册	CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters	2008-6-8
	应用手册	Phase Noise Performance and Jitter Cleaning Ability of CDCE72010	2008-6-2
	应用手册	QFN Layout Guidelines	2006-7-28

设计与开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

评估模块 (EVM) 用 GUI

DATACONVERTERPRO-SW — 高速数据转换器专业 GUI 安装程序，v5.31

该高速数据转换器专业版 GUI 是一款 PC（与 Windows® XP/7/10 兼容）程序，旨在帮助评估大多数 TI 高速数据转换器 [模数转换器 (ADC) 和数模转换器 (DAC)] 和模拟前端 (AFE) 平台。DATACONVERTERPRO-SW 支持整个 TSW14xxx 系列的数据采集和图形生成卡，为分析时域和频域中的数据转换器提供了快速强大的解决方案以及单音、多音和调制信号支持。此 GUI 还兼容用于快速合成单音、多音和调制信号的 TI 图形生成 GUI。

用户可以向 DATACONVERTERPRO-SW 提供自定义图形以加载到 TI DAC。支持从 ADC 捕获导出 (...)

支持的产品和硬件

下载选项

仿真模型