ADS5413
- 12-Bit Resolution
- 65-MSPS Maximum Sample Rate
- 2-Vpp Differential Input Range
- 3.3-V Single Supply Operation
- 1.8-V to 3.3-V Output Supply
- 400-mW Total Power Dissipation
- Twos Complement Output Format
- On-Chip S/H and Duty Cycle Adjust Circuit
- Internal or External Reference
- 48-Pin TQFP Package With PowerPad
(7 mm x 7 mm body size) - 64.5-dBFS SNR and 72-dBc SFDR at 65 MSPS and 190-MHz Input
- Power-Down Mode
- Single-Ended or Differential Clock
- 1-GHz -3-dB Input Bandwidth
- APPLICATIONS
- High IF Sampling Receivers
- Medical Imaging
- Portable Instrumentation
CommsADC is a trademark of Texas Instruments.
The ADS5413 is a low power, 12-bit, 65-MSPS, CMOS pipeline analog-to-digital converter (ADC) that operates from a single 3.3-V supply, while offering the choice of digital output levels from 1.8 V to 3.3 V. The low noise, high linearity, and low clock jitter makes the ADC well suited for high-input frequency sampling applications. On-chip duty cycle adjust circuit allows the use of a non-50% duty cycle. This can be bypassed for applications requiring low jitter or asynchronous sampling. The device can also be clocked with single ended or differential clock, without change in performance. The internal reference can be bypassed to use an external reference to suit the accuracy and low drift requirements of the application.
The device is specified over full temperature range (40°C to +85°C).
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | ADS5413: 12-bit, 65 MSPS CommsADC Analog-to-Digital Converter 数据表 | 2003-12-16 | |||
| 应用手册 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015-5-22 | ||||
| 应用手册 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013-7-19 | ||||
| 应用手册 | High-Speed, Analog-to-Digital Converter Basics | 2012-1-11 | ||||
| 应用手册 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010-9-10 | ||||
| 应用手册 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009-4-28 | ||||
| 应用手册 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008-6-8 | ||||
| 应用手册 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008-6-2 | ||||
| 应用手册 | Standard Procedure Direct Measurement Sub-picosecond RMS Jitter High-Speed ADC | 2004-6-30 | ||||
| 应用手册 | How to Calculate the Period Jitter from the SSCR for High-Speed ADCs | 2003-12-17 |
设计与开发
如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。
ADC-HARMONIC-CALC — ADC Frequency Calculator Download
ADC 谐波计算工具是基于 excel 的计算器,用于确定当模数转换器中出现奈奎斯特混叠后高次谐波的频率空间的位置。
如果给定 ADC 采样速率和有用信号的范围,该计算器可以确定第 2 至第 9 谐波是否会返送到有用信号的频带中。图表以图形方式显示了在出现奈奎斯特混叠后基本信号以及第 2 至第 9 谐波的位置。
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
模拟工程师计算器旨在加快模拟电路设计工程师经常运用的许多重复性计算。该基于 PC 的工具提供图形界面,其中显示各种常见计算列表,从使用反馈电阻器设置运算放大器增益到选择合适的电路设计元件,以稳定模数转换器 (ADC) 驱动器缓冲器电路。
除了可用作独立工具之外,该计算器还能很好地与模拟工程师口袋参考中所述的概念配合使用。
JITTER-SNR-CALC — Jitter and SNR calculator
JITTER-SNR-CALC 可用于根据输入频率和时钟抖动来计算 ADC 的理论信噪比 (SNR) 性能。
SBAC119 — TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| HTQFP (PHP) | 48 | Ultra Librarian |
订购和质量
推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。