ADS5240
- Maximum Sample Rate: 40MSPS
- 12-Bit Resolution
- No Missing Codes
- Total Power Dissipation:
Internal Reference: 584mW
External Reference: 518mW - CMOS Technology
- Simultaneous Sample-and-Hold
- 70.5dBFS SNR at 10MHz IF
- 3.3V Digital/Analog Supply
- Serialized LVDS Outputs
- Integrated Frame and Bit Patterns
- Option to Double LVDS Clock Output Currents
- Four Current Modes for LVDS
- Pin- and Format-Compatible Family
- HTQFP-64 PowerPAD Package
- APPLICATIONS
- Portable Ultrasound Systems
- Tape Drives
- Test Equipment
- Optical Networking
- Communications
PowerPAD Is a trademark of Texas Instruments
All other trademarks are the property of their respective owners
The ADS5240 is a high-performance, 40MSPS, 4-channel analog-to-digital converter (ADC). Internal references are provided, simplifying system design requirements. Low power consumption allows for the highest of system integration densities. Serial LVDS (low-voltage differential signaling) outputs reduce the number of interface lines and package size.
An integrated phase lock loop (PLL) multiplies the incoming ADC sampling clock by a factor of 12. This high-frequency LVDS clock is used in the data serialization and transmission process. The word output of each internal ADC is serialized and transmitted either MSB or LSB first. In addition to the four data outputs, a bit clock and a word clock are also transmitted. The bit clock is at 6x the speed of the sampling clock, whereas the word clock is at the same speed of the sampling clock.
The ADS5240 provides internal references, or can optionally be driven with external references. Best performance can be achieved through the internal reference mode.
The device is available in an HTQFP-64 PowerPAD package and is specified over a -40°C to +85°C operating range.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | 4-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface 数据表 (Rev. E) | 2009-1-6 | |||
| 应用手册 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015-5-22 | ||||
| 应用手册 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013-7-19 | ||||
| 应用手册 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010-9-10 | ||||
| 应用手册 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009-4-28 | ||||
| 应用手册 | CDCE62005 as Clock Solution for High-Speed ADCs | 2008-9-4 | ||||
| 应用手册 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008-6-8 | ||||
| 应用手册 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008-6-2 | ||||
| 应用手册 | Interfacing High-Speed LVDS Outputs of the ADS527x/ADS524x | 2005-2-23 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
ADC-HARMONIC-CALC — ADC Frequency Calculator Download
ADC 谐波计算工具是基于 excel 的计算器，用于确定当模数转换器中出现奈奎斯特混叠后高次谐波的频率空间的位置。
如果给定 ADC 采样速率和有用信号的范围，该计算器可以确定第 2 至第 9 谐波是否会返送到有用信号的频带中。图表以图形方式显示了在出现奈奎斯特混叠后基本信号以及第 2 至第 9 谐波的位置。
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
模拟工程师计算器旨在加快模拟电路设计工程师经常运用的许多重复性计算。该基于 PC 的工具提供图形界面，其中显示各种常见计算列表，从使用反馈电阻器设置运算放大器增益到选择合适的电路设计元件，以稳定模数转换器 (ADC) 驱动器缓冲器电路。
除了可用作独立工具之外，该计算器还能很好地与模拟工程师口袋参考中所述的概念配合使用。
JITTER-SNR-CALC — Jitter and SNR calculator
JITTER-SNR-CALC 可用于根据输入频率和时钟抖动来计算 ADC 的理论信噪比 (SNR) 性能。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| HTQFP (PAP) | 64 | Ultra Librarian |