ADC12D1000RF
- Excellent Noise and Linearity up to and Above fIN =
2.7 GHz - Configurable to Either 3.2 or 2 GSPS Interleaved
or 1600 or 1000 MSPS Dual ADC - New DESCLKIQ Mode for High Bandwidth, High
Sampling Rate Apps - Pin-Compatible With ADC10D1x00, ADC12D1x00
- AutoSync Feature for Multi-Chip Synchronization
- Internally Terminated, Buffered, Differential Analog
Inputs - Interleaved Timing Automatic and Manual Skew
Adjust - Test Patterns at Output for System Debug
- Time Stamp Feature to Capture External Trigger
- Programmable Gain, Offset, and tAD Adjust
Feature - 1:1 Non-Demuxed or 1:2 Demuxed LVDS Outputs
- Key Specifications
- Resolution 12 Bits
- Interleaved 3.2- and 2-GSPS ADC
- IMD3 (Fin = 2.7 GHz at –13 dBFS) –63.7/–73
dBFS (Typical) - IMD3 (Fin = 2.7 GHz at –16 dBFS) –66.7/–85
dBFS (Typical) - Noise Floor –154.6/–154 dBm/Hz (Typical)
- Power 3.94/3.42 W (Typical)
- IMD3 (Fin = 2.7 GHz at –13 dBFS) –63.7/–73
- Dual 1600/1000 MSPS ADC, Fin = 498 MHz
- ENOB 9.2/9.4 Bits (Typical)
- SNR 58.2/58.8 dB (Typical)
- SFDR 66.7/71.9 dBc (Typical)
- Power per Channel 1.97/1.71 W (Typical)
The 12-bit 3.2- and 2-GSPS ADC12D1x00RF is an RF-sampling GSPS ADC that can directly sample input frequencies up to and above 2.7 GHz. The ADC12D1x00RF augments the very large Nyquist zone of TI’s GSPS ADCs with excellent noise and linearity performance at RF frequencies, extending its usable range beyond the 3rd Nyquist zone
The ADC12D1x00RF provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common-mode voltage. The product is packaged in a lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of –40°C to 85°C.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | ADC12D1x00RF 12-Bit, 3.2-GSPS and 2-GSPS RF-Sampling ADC 数据表 (Rev. H) | PDF | HTML | 2015-8-31 | ||
| 应用手册 | AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G) | 2017-2-3 | ||||
| 应用手册 | Signal Chain Noise Figure Analysis | 2014-10-29 | ||||
| 应用手册 | Maximizing SFDR Performance in the GSPS ADC: Spur Sources and Methods of Mitigat | 2013-12-9 | ||||
| 应用手册 | AN-2128 ADC1xD1x00 Pin Compatibility (Rev. C) | 2013-5-1 | ||||
| 用户指南 | Schematic and Layout Recommendations for the GSPS ADC | 2013-4-29 | ||||
| 应用手册 | AN-2177 Using the LMH6554 as a ADC Driver (Rev. A) | 2013-4-26 | ||||
| 应用手册 | From Sample Instant to Data Output: Understanding Latency in the GSPS ADC | 2012-12-18 | ||||
| 产品概述 | ADC12Dxx00RF Direct RF-Sampling ADC Family | 2012-5-16 |
设计与开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
WAVEVISION5 — WaveVision 5 Software
WaveVision 5 software is part of the WaveVision evaluation system that also includes WaveVision 5 Data Capture Board. The WaveVision 5 system is an easy-to-use data acquisition and analysis tool, designed to help users evaluate Texas Instruments' Signal Path solutions.
While WaveVision 5 software (...)
TIDA-00113 — 在单通道模式或双通道模式下针对高带宽应用驱动 GSPS ADC
该设计旨在帮助系统设计人员权衡利弊，推动具有每秒千兆取样率的 ADC（采用平衡-非平衡变压器配置）在带宽应用中的应用，并对该实施过程进行优化。需考虑的权衡因素包括平衡-非平衡变压器的结构、插入损耗、动态性能、可配置性和实施的简便性。拓扑和布局在优化系统性能的过程中尤为重要，这也正是这些设计能够有助于缩短设计周期的原因所在。
TIDA-00479 — GSPS ADC 的理想时钟源参考设计
ADC12D1600RFRB 参考设计提供了一个可展示高速数字转换器应用（其中整合了时钟、电源管理和信号处理）的平台。该参考设计采用 1.6GSPS ADC12D1600RF 器件、板载 FPGA Xilinx Virtex 4 和高性能时钟合成器 LMX2531，以满足 9 位 ENOB 高速数字转换器的系统要求。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| PBGA (NXA) | 292 | Ultra Librarian |
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