ADC10D1000
- Excellent Accuracy and Dynamic Performance
- Pin Compatible with ADC12D1000/1600/1800
- Low Power Consumption, Further Reduced at Lower Fs
- Internally Terminated, Buffered, Differential Analog Inputs
- R/W SPI Interface for Extended Control Mode
- Dual-Edge Sampling Mode, in Which the I- and Q-channels Sample One Input at Twice the Sampling Clock Rate
- Test Patterns at Output for System Debug
- Programmable 15-bit Gain and 12-bit Plus Sign Offset
- Programmable tAD Adjust Feature
- 1:1 Non-demuxed or 1:2 Demuxed LVDS Outputs
- AutoSync Feature for Multi-Chip Systems
- Single 1.9V ± 0.1V Power Supply
- 292-Ball BGA Package (27mm x 27mm x 2.4mm with 1.27mm Ball-Pitch); No Heat Sink Required
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The ADC10D1000/1500 is the latest advance in TI's Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.0/1.5 GSPS (Non-DES Mode) or for a single channel up to 2.0/3.0 GSPS (DES Mode). The ADC10D1000/1500 achieves excellent accuracy and dynamic performance while dissipating less than 2.8/3.6 Watts. The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C.
The ADC10D1000/1500 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. An expanded feature set includes AutoSync for multi-chip synchronization, 15-bit programmable gain and 12-bit plus sign programmable offset adjustment for each channel. The improved internal track-and-hold amplifier and the extended self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing 9.1/9.0 Effective Number of Bits (ENOB) with a 100 MHz input signal and a 1.0/1.5 GHz sample rate while providing a 10-18 Code Error Rate (CER) Dissipating a typical 2.77/3.59 Watts in Non-Demultiplex Mode at 1.0/1.5 GSPS from a single 1.9V supply, this device is specified to have no missing codes over the full operating temperature range.
Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demux Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower to relax data-capture timing requirements. The part can also be used as a single 2.0/3.0 GSPS ADC to sample one of the I or Q inputs. The output formatting can be programmed to be offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V to allow for power reduction for well-controlled back planes.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | ADC10D1000/1500 Low Power, 10-Bit, Dual 1.0/1.5 GSPS or Single 2.0/3.0 GSPS ADC 数据表 (Rev. Q) | 2013-3-15 | |||
| 应用手册 | AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G) | 2017-2-3 | ||||
| 应用手册 | Maximizing SFDR Performance in the GSPS ADC: Spur Sources and Methods of Mitigat | 2013-12-9 | ||||
| 应用手册 | AN-2128 ADC1xD1x00 Pin Compatibility (Rev. C) | 2013-5-1 | ||||
| 用户指南 | Schematic and Layout Recommendations for the GSPS ADC | 2013-4-29 | ||||
| 应用手册 | AN-2177 Using the LMH6554 as a ADC Driver (Rev. A) | 2013-4-26 | ||||
| 应用手册 | From Sample Instant to Data Output: Understanding Latency in the GSPS ADC | 2012-12-18 |
设计与开发
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ADC-LD-BB — ADC 低失真平衡-非平衡转换板
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顺带一提，该平衡-非平衡转换板也可用于进行差分至单端转换。例如，在单端示波器上观察 DCLK± 或 RCOut± 信号时，可使用此平衡-平衡转换板来探索 GSPS ADC 参考板的自动同步功能。
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TIDA-00113 — 在单通道模式或双通道模式下针对高带宽应用驱动 GSPS ADC
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| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| PBGA (NXA) | 292 | Ultra Librarian |
订购和质量
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