ADC081000
- Internal Sample-and-Hold
- Single +1.9V ±0.1V Operation
- Adjustable Output Levels
- Ensured No Missing Codes
- Low Power Standby Mode
The ADC081000 is a low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 1.6 GSPS. Consuming a typical 1.4 Watts at 1 GSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 500 MHz input signal and a 1 GHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compliant with IEEE 1596.3-1996, with the exception of a reduced common mode voltage of 0.8V.
The converter has a 1:2 demultiplexer that feeds two LVDS buses, reducing the output data rate on each bus to half the sampling rate. The data on these buses are interleaved in time to provide a 500 MHz output rate per bus and a combined output rate of 1 GSPS.
The converter typically consumes less than 10 mW in the Power Down Mode and is available in a 128-lead HLQFP and operates over the industrial (–40°C ≤ TA ≤ +85°C) temperature range.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | ADC081000 High-Performance Low-Power 8-Bit 1-GSPS ADC 数据表 (Rev. G) | 2013-5-2 | |||
| 应用手册 | Generating Precision Clocks for Time- Interleaved ADCs | 2007-8-2 | ||||
| 白皮书 | Interleaving ADCs for Higher Sample Rates | 2005-2-1 | ||||
| 白皮书 | Ultra-High Speed ADCs Revolutionize Digital Receiver Design | 2004-2-1 |
设计与开发
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| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| HLQFP (NNB) | 128 | Ultra Librarian |