ADC3648

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250-MSPS-ADC, 14 Bit, 2 Kanäle, mit LVDS-Schnittstelle und bis zu 32768x Dezimation

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Datenblatt

document-pdfAcrobat ADC364x Dual-Channel, 14-Bit 250MSPS and 500MSPS Analog-to-Digital Converter (ADC) datasheet (Rev. B) (Englisch) PDF | HTML

ADC3648

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Sample rate (max) (Msps)

250

Resolution (Bits)

14

Number of input channels

2

Interface type

DDR LVDS

Analog input BW (MHz)

1400

Features

Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Input buffer, Low latency, Low power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

470

Architecture

Pipeline

SNR (dB)

74

ENOB (Bits)

12

SFDR (dB)

83

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

Sample rate (max) (Msps)

250

Resolution (Bits)

14

Number of input channels

2

Interface type

DDR LVDS

Analog input BW (MHz)

1400

Features

Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Input buffer, Low latency, Low power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

470

Architecture

Pipeline

SNR (dB)

74

ENOB (Bits)

12

SFDR (dB)

83

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

VQFNP (RTD)

64

81 mm² 9 x 9

14-bit, dual channel 250 and 500MSPS ADC
Noise spectral density: -158.5dBFS/Hz
Thermal Noise: 74.5dBFS
Single core (non-interleaved) ADC architecture
Power consumption:
- 300mW/channel (500MSPS)
- 250mW/channel (250MSPS)
Aperture jitter: 75fs
Buffered analog inputs
- Programmable 100Ω to 200Ω termination
Input full scale: 2Vpp
Full power input bandwidth (-3dB): 1.4GHz
Spectral performance (fIN = 70MHz, -1dBFS):
- SNR: 73.8dBFS
- SFDR HD2,3: 84dBc
- SFDR worst spur: 90dBFS
Digital down-converters (DDCs)
- Up to four independent DDCs
- Complex and real decimation
- Decimation: /2, /4 to /32768 decimation
- 48-bit NCO phase coherent frequency hopping
DDR, Serial LVDS interface
- 14-bit Parallel DDR LVDS for DDC bypass
- 16-bit Serial LVDS for decimation
- 32-bit output option for high decimation

14-bit, dual channel 250 and 500MSPS ADC
Noise spectral density: -158.5dBFS/Hz
Thermal Noise: 74.5dBFS
Single core (non-interleaved) ADC architecture
Power consumption:
- 300mW/channel (500MSPS)
- 250mW/channel (250MSPS)
Aperture jitter: 75fs
Buffered analog inputs
- Programmable 100Ω to 200Ω termination
Input full scale: 2Vpp
Full power input bandwidth (-3dB): 1.4GHz
Spectral performance (fIN = 70MHz, -1dBFS):
- SNR: 73.8dBFS
- SFDR HD2,3: 84dBc
- SFDR worst spur: 90dBFS
Digital down-converters (DDCs)
- Up to four independent DDCs
- Complex and real decimation
- Decimation: /2, /4 to /32768 decimation
- 48-bit NCO phase coherent frequency hopping
DDR, Serial LVDS interface
- 14-bit Parallel DDR LVDS for DDC bypass
- 16-bit Serial LVDS for decimation
- 32-bit output option for high decimation

The ADC3648 and ADC3649 (ADC364x) are a 14-bit, 250MSPS and 500MSPS, dual channel analog to digital converter (ADC). The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of -158.5dBFS/Hz (500MSPS).

The power efficient ADC architecture consumes 300mW/ch at 500MSPS and provides power scaling with lower sampling rates (250mW/ch at 250MSPS).

The ADC364x includes an optional quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.

The ADC364x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a 14-bit wide parallel DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation rates, the output resolution can be increased to 32-bit.

The ADC3648 and ADC3649 (ADC364x) are a 14-bit, 250MSPS and 500MSPS, dual channel analog to digital converter (ADC). The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of -158.5dBFS/Hz (500MSPS).

The power efficient ADC architecture consumes 300mW/ch at 500MSPS and provides power scaling with lower sampling rates (250mW/ch at 250MSPS).

The ADC364x includes an optional quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.

The ADC364x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a 14-bit wide parallel DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation rates, the output resolution can be increased to 32-bit.

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Top-Dokumentation	Typ	Titel	Format-Optionen	Datum
*	Data sheet	ADC364x Dual-Channel, 14-Bit 250MSPS and 500MSPS Analog-to-Digital Converter (ADC) datasheet (Rev. B)	PDF \| HTML	05 Jun 2025
	Analog Design Journal	Sampling around Nyquist holes in high-speed converters	PDF \| HTML	16 Mai 2025
	Application note	Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends	PDF \| HTML	28 Mär 2025
	Application note	Evaluating High-Speed, RF ADC Converter Front-end Architectures	PDF \| HTML	26 Mär 2025
	Application note	Improving MSPS ADC’s SFDR While Relaxing AAF Requirements and Using Integrated DDC Features	PDF \| HTML	18 Feb 2025

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Evaluierungsplatine

ADC3669EVM — ADC3669 – Evaluierungsmodul

Mit dem Evaluierungsmodul (EVM) ADC3669EVM kann die ADC3669-Familie von Hochgeschwindigkeits-ADCs bewertet werden. ADC3669EVM ist mit einem ADC3669 bestückt. ADC3669 ist ein 16-Bit-Dual-Kanal-ADC mit LVDS-Schnittstelle, der mit Sample-Raten von bis zu 500 MSPS arbeiten kann. ADC3669EVM ermöglicht (...)

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ADC3669-NOISE-ANALYSIS-CALC — Noise analysis calculation tool (SNR/SFDR) for ADC3669 with amplifier input.

Calculation tool for analyzing noise of ADC3669 with an amplifier as the input network.

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ADC3648

250-MSPS-ADC, 14 Bit, 2 Kanäle, mit LVDS-Schnittstelle und bis zu 32768x Dezimation

ADC3648

Produktdetails

Technische Dokumentation

Design und Entwicklung

ADC3669EVM — ADC3669 – Evaluierungsmodul

ADC3669-NOISE-ANALYSIS-CALC — Noise analysis calculation tool (SNR/SFDR) for ADC3669 with amplifier input.

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PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool

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Download-Möglichkeiten

ADC3669-NOISE-ANALYSIS-CALC — Noise analysis calculation tool (SNR/SFDR) for ADC3669 with amplifier input.

Highspeed-ADCs (≥ 10 MSPS)

HF-Volldifferenzverstärker (FDAs)

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