10MHz 至 135MHz、28 位 LVDS 变送器/串行器与 FlatLink™ 集成电路




Function Serializer Rating Catalog Operating temperature range (C) -10 to 70 open-in-new 查找其它 显示 SerDes


TSSOP (DGG) 56 113 mm² 14 x 8.1 open-in-new 查找其它 显示 SerDes


  • LVDS Display Series Interfaces Directly to LCD
    Display Panels With Integrated LVDS
  • Package Options: 4.5-mm × 7-mm BGA,
    and 8.1-mm × 14-mm TSSOP
  • 1.8-V Up to 3.3-V Tolerant Data Inputs to Connect
    Directly to Low-Power, Low-Voltage Application and
    Graphic Processors
  • Transfer Rate up to 135 Mpps (Mega Pixel Per Second);
    Pixel Clock Frequency Range 10 MHz to 135 MHz
  • Suited for Display Resolutions Ranging From HVGA
    up to HD With Low EMI
  • Operates From a Single 3.3-V Supply and 170 mW (Typ.)
    at 75 MHz
  • 28 Data Channels Plus Clock in Low-Voltage TTL to 4
    Data Channels Plus Clock Out Low-Voltage Differential
  • Consumes Less Than 1 mW When Disabled
  • Selectable Rising or Falling Clock Edge Triggered
  • ESD: 5-kV HBM
  • Support Spread Spectrum Clocking (SSC)
  • Compatible with all OMAP™ 2x, OMAP™ 3x, and
    DaVinci™ Application Processors
open-in-new 查找其它 显示 SerDes


The SN75LVDS83B FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN75LVDS83B requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level.

The SN75LVDS83B is characterized for operation over ambient air temperatures of –10°C to 70°C.

Alternative device option: The SN75LVDS83A (SLLS980) is an alternative to the SN75LVDS83B for clock frequency range of 10MHz-100MHz only. The SN75LVDS83A is available in the TSSOP package option only.

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类型 标题 下载最新的英文版本 发布
* 数据表 SN75LVDS83B FlatLink™ Transmitter 数据表 2014年 7月 29日
应用手册 AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines 2018年 8月 3日
应用手册 How to Bridge HDMI/DVI to LVDS/OLDI 2018年 6月 7日
技术文章 Applications of Low Voltage Differential Signaling (LVDS) in Multifunction and Industrial Printers 2017年 8月 24日
应用手册 FlatLink™ Data Transmission System Using SN75LVDS83B/SN75LVDS82/SN75LVDS86A 2010年 2月 2日




评估板 下载

J6Entry/RSP EVM 是一种评估平台,用于加快信息娱乐系统、可重新配置的数字群集或集成数字化驾驶舱等应用的开发速度,并缩短其上市时间。

主 CPU 板集成了以太网或 HDMI 等主要外设,而信息娱乐应用子板 (JAMR3) 和 LCD/TS 子板将补充 CPU 板,从而提供完整的系统以快速开始评估和应用开发。

  • 具有电容式触控功能的 10.1" 显示
  • JAMR3 无线电调谐器应用板
  • 2GB DDR3L
  • LP8733/LP8732 电源解决方案
  • 板载 eMMC、NAND、NOR
  • USB3、USB2、PCIe、以太网、COM8Q、CAN、MLB、MicroSD 和 HDMI 连接器
评估板 下载
显示应用板是一种可作为显示及多触控触控屏子板的用于 J6Entry、RSP 和 TDA2E-17 CPU EVM 板的应用板
  • 具有电容式多触控功能的 10.1" AUO 显示 (1280X800)
  • 可连接到 CPU 板 EVM 的 24 位并行接口
评估板 下载
document-generic 用户指南
SN75LVDS83B 变送器在单个集成电路中包含 4 个 7 位并行负载串行输出相移寄存器、1 个 7X 时钟合成器以及 5 个低电压差动信号 (LVDS) 线路驱动器。借助这些功能,可通过 5 个平衡对导体将 28 位单端 LVTTL 数据同步发送至兼容接收器,如 SN75LVDS82 和具有集成 LVDS 接收器的 LCD 面板。该 EVM 同样适用于评估 SN65LVDS93A 和 SN65LVDS93A-Q1 器件。
  • 即插即用设计
  • 使用 USB VBUS 或 5V 至 5.5V 直流输入(通过电源插孔 J3)为 EVM 供电
  • 可通过接头检修 I2C 总线
  • 可通过 DIP 开关进行配置


仿真模型 下载
SLLM077.ZIP (31 KB) - IBIS Model
仿真工具 下载
document-generic 用户指南 document-generic 下载英文版本 (Rev.A)


参考设计 下载
适用于 Sitara™ 处理器的 RGB 转 OLDI/LVDS 显示桥接参考设计
TIDA-010013 — Higher resolution displays are now in larger demand than ever before. This results in a higher pixel clock which can lead to challenges such as high EMI emission and noise immunity. As a result, the video interface now transitions from a traditional RGB to LVDS video interface. As microprocessors (...)
document-generic 原理图 document-generic 用户指南 document-generic 下载英文版本


封装 引脚 下载
TSSOP (DGG) 56 了解详情



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