SN75LVDS83B

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10MHz 至 135MHz、28 位 LVDS 变送器/串行器与 FlatLink™ 集成电路

产品详情

Protocols Catalog Rating Catalog Operating temperature range (°C) -10 to 70
Protocols Catalog Rating Catalog Operating temperature range (°C) -10 to 70
TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • LVDS Display Series Interfaces Directly to LCD
    Display Panels With Integrated LVDS
  • Package Options: 4.5-mm × 7-mm BGA,
    and 8.1-mm × 14-mm TSSOP
  • 1.8-V Up to 3.3-V Tolerant Data Inputs to Connect
    Directly to Low-Power, Low-Voltage Application and
    Graphic Processors
  • Transfer Rate up to 135 Mpps (Mega Pixel Per Second);
    Pixel Clock Frequency Range 10 MHz to 135 MHz
  • Suited for Display Resolutions Ranging From HVGA
    up to HD With Low EMI
  • Operates From a Single 3.3-V Supply and 170 mW (Typ.)
    at 75 MHz
  • 28 Data Channels Plus Clock in Low-Voltage TTL to 4
    Data Channels Plus Clock Out Low-Voltage Differential
  • Consumes Less Than 1 mW When Disabled
  • Selectable Rising or Falling Clock Edge Triggered
    Inputs
  • ESD: 5-kV HBM
  • Support Spread Spectrum Clocking (SSC)
  • Compatible with all OMAP™ 2x, OMAP™ 3x, and
    DaVinci™ Application Processors
  • LVDS Display Series Interfaces Directly to LCD
    Display Panels With Integrated LVDS
  • Package Options: 4.5-mm × 7-mm BGA,
    and 8.1-mm × 14-mm TSSOP
  • 1.8-V Up to 3.3-V Tolerant Data Inputs to Connect
    Directly to Low-Power, Low-Voltage Application and
    Graphic Processors
  • Transfer Rate up to 135 Mpps (Mega Pixel Per Second);
    Pixel Clock Frequency Range 10 MHz to 135 MHz
  • Suited for Display Resolutions Ranging From HVGA
    up to HD With Low EMI
  • Operates From a Single 3.3-V Supply and 170 mW (Typ.)
    at 75 MHz
  • 28 Data Channels Plus Clock in Low-Voltage TTL to 4
    Data Channels Plus Clock Out Low-Voltage Differential
  • Consumes Less Than 1 mW When Disabled
  • Selectable Rising or Falling Clock Edge Triggered
    Inputs
  • ESD: 5-kV HBM
  • Support Spread Spectrum Clocking (SSC)
  • Compatible with all OMAP™ 2x, OMAP™ 3x, and
    DaVinci™ Application Processors

The SN75LVDS83B FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN75LVDS83B requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level.

The SN75LVDS83B is characterized for operation over ambient air temperatures of –10°C to 70°C.

Alternative device option: The SN75LVDS83A (SLLS980) is an alternative to the SN75LVDS83B for clock frequency range of 10MHz-100MHz only. The SN75LVDS83A is available in the TSSOP package option only.

The SN75LVDS83B FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN75LVDS83B requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level.

The SN75LVDS83B is characterized for operation over ambient air temperatures of –10°C to 70°C.

Alternative device option: The SN75LVDS83A (SLLS980) is an alternative to the SN75LVDS83B for clock frequency range of 10MHz-100MHz only. The SN75LVDS83A is available in the TSSOP package option only.

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类型 标题 下载最新的英语版本 日期
* 数据表 SN75LVDS83B FlatLink™ Transmitter 数据表 (Rev. C) PDF | HTML 2014年 7月 29日
应用手册 AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (Rev. A) 2018年 8月 3日
应用手册 How to Bridge HDMI/DVI to LVDS/OLDI (Rev. C) 2018年 6月 7日
技术文章 Applications of Low Voltage Differential Signaling (LVDS) in Multifunction and Ind PDF | HTML 2017年 8月 24日
应用手册 FlatLink™ Data Transmission System Using SN75LVDS83B/SN75LVDS82/SN75LVDS86A 2010年 2月 2日

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评估板

EVMX777G-01-20-00 — J6Entry/RSP 信息娱乐(CPU + 显示屏 + JAMR3)评估模块

J6Entry/RSP EVM 是一种评估平台,用于加快信息娱乐系统、可重新配置的数字群集或集成数字化驾驶舱等应用的开发速度,并缩短其上市时间。

主 CPU 板集成了以太网或 HDMI 等主要外设,而信息娱乐应用子板 (JAMR3) 和 LCD/TS 子板将补充 CPU 板,从而提供完整的系统以快速开始评估和应用开发。

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LVDS83BTSSOPEVM — LVDS83BT 10-135MHz 28 位 LVDS 变送器/串行器评估模块

SN75LVDS83B 变送器在单个集成电路中包含 4 个 7 位并行负载串行输出相移寄存器、1 个 7X 时钟合成器以及 5 个低电压差动信号 (LVDS) 线路驱动器。借助这些功能,可通过 5 个平衡对导体将 28 位单端 LVTTL 数据同步发送至兼容接收器,如 SN75LVDS82 和具有集成 LVDS 接收器的 LCD 面板。该 EVM 同样适用于评估 SN65LVDS93A 和 SN65LVDS93A-Q1 器件。
用户指南: PDF
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仿真模型

SN75LVDS83B IBIS Model

SLLM077.ZIP (31 KB) - IBIS Model
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用户指南: PDF
英语版 (Rev.A): PDF
参考设计

TIDA-010013 — 适用于 Sitara™ 处理器的 RGB 转 OLDI/LVDS 显示桥接参考设计

Higher resolution displays are now in larger demand than ever before. This results in a higher pixel clock which can lead to challenges such as high EMI emission and noise immunity. As a result, the video interface now transitions from a traditional RGB to LVDS video interface. As microprocessors (...)
设计指南: PDF
原理图: PDF
封装 引脚 CAD 符号、封装和 3D 模型
TSSOP (DGG) 56 Ultra Librarian

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