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逻辑和电压转换
触发器、锁存器和寄存器
电压转换触发器、锁存器和寄存器

SN74LV8T374

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具有三态输出和集成电平转换功能的八通道边沿触发式 D 类触发器

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SN74LV8T374

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产品详情

Operating temperature range (°C) to
Operating temperature range (°C) to
VQFN (RKS) 20 11.25 mm² (4.5 mm × 2.5 mm) VSSOP (DGS) 20 24.99 mm² (5.1 mm × 4.9 mm) TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm)
  • Wide operating range of 1.65V to 5.5V
  • 5.5V tolerant input pins
  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
    • Up translation:
      • 1.2V to 1.8V
      • 1.5V to 2.5V
      • 1.8V to 3.3V
      • 3.3V to 5.0V

    • Down translation:

      • 5.0V, 3.3V, 2.5V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • Up to 150Mbps with 5V or 3.3V VCC
  • Supports standard function pinout
  • Latch-up performance exceeds 250mAper JESD 17
  • Wide operating range of 1.65V to 5.5V
  • 5.5V tolerant input pins
  • Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
    • Up translation:
      • 1.2V to 1.8V
      • 1.5V to 2.5V
      • 1.8V to 3.3V
      • 3.3V to 5.0V

    • Down translation:

      • 5.0V, 3.3V, 2.5V to 1.8V
      • 5.0V, 3.3V to 2.5V
      • 5.0V to 3.3V
  • Up to 150Mbps with 5V or 3.3V VCC
  • Supports standard function pinout
  • Latch-up performance exceeds 250mAper JESD 17

The SN74LV8T374 contains eight D-type flip-flops. All channels share a rising edge triggered clock (CLK) input and active low output enable (OE) input. This device has a flow-through pinout which allows for easier bus routing.

The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The SN74LV8T374 contains eight D-type flip-flops. All channels share a rising edge triggered clock (CLK) input and active low output enable (OE) input. This device has a flow-through pinout which allows for easier bus routing.

The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
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SN74AHCT374 正在供货 具有三态输出的八路边沿触发式 D 型触发器 Voltage range 4.5V to 5.5V, average propagation delay 9ns, average drive strength 8mA

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* 数据表 SN74LV8T374 Translating Octal D-Type Flip-Flops with Clear 数据表 PDF | HTML 2025-7-1

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14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块

14-24-LOGIC-EVM 评估模块 (EVM) 设计用于支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。

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评估板

14-24-NL-LOGIC-EVM — 采用 14 引脚至 24 引脚无引线封装的逻辑产品通用评估模块

14-24-EVM 是一款灵活的评估模块 (EVM)，旨在支持具有 14 引脚至 24 引脚 BQA、BQB、RGY、RSV、RJW 或 RHL 封装的任何逻辑或转换器件。

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封装 引脚 CAD 符号、封装和 3D 模型
VQFN (RKS) 20 Ultra Librarian
VSSOP (DGS) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

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