SN74LV86A
- 2-V to 5.5-V VCC Operation
- Max tpd of 8 ns at 5 V
- Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot) >2.3 V
at VCC = 3.3 V, TA = 25°C - Support Mixed-Mode Voltage Operation on All Ports
- Latch-Up Performance Exceeds 250 mA per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
The ’LV86A devices are quadruple 2-input exclusive-OR gates designed for 2-V to 5.5-V VCC operation.
These devices contain four independent 2-input exclusive-OR gates. They perform the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic.
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output.
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| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | SNx4LV86A Quadruple 2-Input Exclusive-OR Gates 数据表 (Rev. G) | PDF | HTML | 2015-2-11 |
设计与开发
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评估板
14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块
14-24-LOGIC-EVM 评估模块 (EVM) 设计用于支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| SOP (NS) | 14 | Ultra Librarian |
| TSSOP (PW) | 14 | Ultra Librarian |
| SOIC (D) | 14 | Ultra Librarian |
| TVSOP (DGV) | 14 | Ultra Librarian |
| SSOP (DB) | 14 | Ultra Librarian |