SN74FB1653
- Compatible With IEEE Std 1194.1-1991 (BTL)
- LVTTL A Port, Backplane Transceiver Logic (BTL) B\ Port
- Open-Collector B\-Port Outputs Sink 100 mA
- B\-Port Biasing Network Preconditions the Connector and PC Trace to the BTL High-Level Voltage
- High-Impedance State During Power Up and Power Down
- Selectable Clock Delay
- TTL-Input Structures Incorporate Active Clamping Networks to Aid in Line Termination
- BIAS VCC Minimizes Signal Distortion During Live Insertion/Withdrawal
The SN74FB1653 contains an 8-bit and a 9-bit transceiver with a buffered clock. The clock and transceivers are designed to translate signals between LVTTL and BTL environments. The device is designed specifically to be compatible with IEEE Std 1194.1-1991 (BTL).
The A port operates at LVTTL signal levels. The A outputs reflect the inverse of the data at the B\ port when the A-port output enable (OEA) is high. When OEA is low or when VCC(5 V) typically is less than 2.5 V, the A outputs are in the high-impedance state.
The B\ port operates at BTL signal levels. The open-collector B\ ports are specified to sink 100 mA. Two output enables (OEB and OEB)\ are provided for the B\ outputs. When OEB is low, OEB\ is high, or VCC(5 V) typically is less than 2.5 V, the B port is turned off.
The clock-select (2SEL1 and 2SEL2) inputs are used to configure the TTL-to-BTL clock paths and delays (refer to the MUX-MODE DELAY table).
BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC(5 V) is not connected.
BG VCC and BG GND are the supply inputs for the bias generator.
VREF is an internally generated voltage source. It is recommended that VREF be decoupled with a 0.1-µF capacitor.
Enhanced heat-dissipation techniques should be used when operating this device from AI to A0 at frequencies greater than 50 MHz, or from AI to B\ or B\ to A0 at frequencies greater than 100 MHz.
技术文档
类型 | 标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | SN74FB1653 数据表 (Rev. H) | 2004年 3月 10日 | |||
应用手册 | Implications of Slow or Floating CMOS Inputs (Rev. E) | 2021年 7月 26日 | ||||
选择指南 | Voltage Translation Buying Guide (Rev. A) | 2021年 4月 15日 | ||||
选择指南 | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||||
应用手册 | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||||
选择指南 | 逻辑器件指南 2014 (Rev. AA) | 最新英语版本 (Rev.AB) | 2014年 11月 17日 | |||
选择指南 | 《高级总线接口逻辑器件选择指南》 | 英语版 | 2010年 7月 7日 | |||
用户指南 | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||||
应用手册 | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||||
应用手册 | TI IBIS File Creation, Validation, and Distribution Processes | 2002年 8月 29日 | ||||
应用手册 | Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices | 2002年 5月 10日 | ||||
应用手册 | GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic (Rev. A) | 1997年 3月 1日 | ||||
应用手册 | Next-Generation BTL/Futurebus Transceivers Allow Single-Sided SMT Manufacturing (Rev. C) | 1997年 3月 1日 | ||||
应用手册 | Understanding Advanced Bus-Interface Products Design Guide | 1996年 5月 1日 |
设计和开发
如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。
封装 | 引脚 | 下载 |
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HLQFP (PCA) | 100 | 查看选项 |
订购和质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
- 鉴定摘要
- 持续可靠性监测
- 制造厂地点
- 封装厂地点