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SN74AXCH8T245 正在供货 8 位双电源总线收发器 Pin-to-pin upgrade with a wider voltage range and improved performance

产品详情

Technology family AVC Bits (#) 8 High input voltage (min) (V) 1.2 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (MBps) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 16 Features Bus-hold, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AVC Bits (#) 8 High input voltage (min) (V) 1.2 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (MBps) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 16 Features Bus-hold, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4 TVSOP (DGV) 24 32 mm² 5 x 6.4 VQFN (RHL) 24 19.25 mm² 5.5 x 3.5
  • Control Inputs (DIR and OE) VIH and VIL Levels Are Referenced to VCCA Voltage
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup or Pulldown Resistors
  • VCC Isolation Feature
  • Fully Configurable Dual-Rail Design
  • I/Os Are 4.6-V Tolerant
  • Ioff Supports Partial-Power-Down Mode Operation
  • Max Data Rates:
    • 320 Mbps (VCCA ≥ 1.8 V and VCCB ≥ 1.8 V)
    • 170 Mbps (VCCA ≤ 1.8 V or VCCB ≤ 1.8 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 8000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Control Inputs (DIR and OE) VIH and VIL Levels Are Referenced to VCCA Voltage
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup or Pulldown Resistors
  • VCC Isolation Feature
  • Fully Configurable Dual-Rail Design
  • I/Os Are 4.6-V Tolerant
  • Ioff Supports Partial-Power-Down Mode Operation
  • Max Data Rates:
    • 320 Mbps (VCCA ≥ 1.8 V and VCCB ≥ 1.8 V)
    • 170 Mbps (VCCA ≤ 1.8 V or VCCB ≤ 1.8 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 8000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

The SN74AVCH8T245 is an 8-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The A port is designed to track VCCA, which accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB, which also accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCH8T245 is designed for asynchronous communication between data buses. The device transmits data from either the A bus to the B bus, or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated.

The SN74AVCH8T245 is designed so that the control pins (DIR and OE) are referenced to VCCA.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device.

The VCC isolation feature ensures that if either VCCA or VCCB is at GND, then the outputs are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active.

The SN74AVCH8T245 solution is compatible with a single-supply system and can be replaced later with a ’245 function, with minimal printed circuit board redesign.

To ensure the high-impedance state during power up or power down, OE shall be tied to VCCA through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74AVCH8T245 is an 8-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The A port is designed to track VCCA, which accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB, which also accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCH8T245 is designed for asynchronous communication between data buses. The device transmits data from either the A bus to the B bus, or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated.

The SN74AVCH8T245 is designed so that the control pins (DIR and OE) are referenced to VCCA.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device.

The VCC isolation feature ensures that if either VCCA or VCCB is at GND, then the outputs are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active.

The SN74AVCH8T245 solution is compatible with a single-supply system and can be replaced later with a ’245 function, with minimal printed circuit board redesign.

To ensure the high-impedance state during power up or power down, OE shall be tied to VCCA through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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技术文档

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类型 项目标题 下载最新的英语版本 日期
* 数据表 SN74AVCH8T245 8-Bit Dual-Supply Bus Transceiver With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs 数据表 (Rev. H) PDF | HTML 2016年 4月 1日
选择指南 Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
应用手册 Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015年 4月 30日
选择指南 逻辑器件指南 2014 (Rev. AA) 下载最新的英文版本 (Rev.AB) 2014年 11月 17日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 选择正确的电平转换解决方案 (Rev. A) 下载英文版本 (Rev.A) 2006年 3月 23日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
更多文献资料 LCD Module Interface Application Clip 2003年 5月 9日
用户指南 AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 2002年 8月 20日
更多文献资料 Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
应用手册 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
应用手册 Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 1999年 7月 7日
应用手册 AVC Logic Family Technology and Applications (Rev. A) 1998年 8月 26日

设计和开发

如需其他信息或资源,请查看下方列表,点击标题即可进入详情页面。

评估板

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该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。

用户指南: PDF | HTML
下载英文版本 (Rev.B): PDF | HTML
TI.com 上无现货
评估板

14-24-NL-LOGIC-EVM — 通用 14 至 24 引脚无铅封装评估模块

Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
用户指南: PDF | HTML
下载英文版本 (Rev.A): PDF | HTML
TI.com 上无现货
评估板

AVCLVCDIRCNTRL-EVM — 适用于方向控制双向转换器件、支持 AVC 和 LVC 的通用 EVM

该通用 EVM 旨在支持 1、2、4 和 8 通道 LVC 和 AVC 方向控制转换器件。它还以相同数量的通道支持总线保持和汽车 Q1 器件。AVC 是低电压转换器件,具有 12mA 的较低驱动强度。LVC 是 1.65 至 5.5V 的较高电压转换器件,具有 32mA 的较高驱动强度。

用户指南: PDF | HTML
下载英文版本 (Rev.B): PDF | HTML
TI.com 上无现货
仿真模型

SN74AVCH8T245 IBIS Model

SCEM426.ZIP (68 KB) - IBIS Model
封装 引脚数 下载
TSSOP (PW) 24 了解详情
TVSOP (DGV) 24 了解详情
VQFN (RHL) 24 了解详情

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

支持与培训

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