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方向控制型电压转换器

SN74AVC4T245

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具有可配置电压转换和三态输出的 4 位双电源总线收发器

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SN74AXC4T245 正在供货 4 位双电源总线收发器 Pin-to-pin upgrade with a wider voltage range and improved performance

SN74AVC4T245

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产品详情

Technology family AVC Applications ART, JTAG, SPI Bits (#) 4 High input voltage (min) (V) 0.78 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (MBits) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 16 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AVC Applications ART, JTAG, SPI Bits (#) 4 High input voltage (min) (V) 0.78 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (MBits) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 16 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 16 59.4 mm² 9.9 x 6 TSSOP (PW) 16 32 mm² 5 x 6.4 TVSOP (DGV) 16 23.04 mm² 3.6 x 6.4 UQFN (RSV) 16 4.68 mm² 2.6 x 1.8 VQFN (RGY) 16 14 mm² 4 x 3.5
  • Control Inputs VIH/VIL Levels Are
    Referenced to VCCA Voltage
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate
    Over the Full 1.2-V to 3.6-V Power-Supply Range
  • I/Os Are 4.6-V Tolerant
  • Ioff Supports Partial Power-Down-Mode Operation
  • Maximum Data Rates
    • 380 Mbps (1.8-V to 3.3-V Translation)
    • 200 Mbps (< 1.8-V to 3.3-V Translation)
    • 200 Mbps (Translate to 2.5 V or 1.8 V)
    • 150 Mbps (Translate to 1.5 V)
    • 100 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 8000-V Human-Body Model (A114-A)
    • 150-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Control Inputs VIH/VIL Levels Are
    Referenced to VCCA Voltage
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate
    Over the Full 1.2-V to 3.6-V Power-Supply Range
  • I/Os Are 4.6-V Tolerant
  • Ioff Supports Partial Power-Down-Mode Operation
  • Maximum Data Rates
    • 380 Mbps (1.8-V to 3.3-V Translation)
    • 200 Mbps (< 1.8-V to 3.3-V Translation)
    • 200 Mbps (Translate to 2.5 V or 1.8 V)
    • 150 Mbps (Translate to 1.5 V)
    • 100 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 8000-V Human-Body Model (A114-A)
    • 150-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This 4-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. The SN74AVC4T245 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVC4T245 device is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC4T245 device is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This 4-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. The SN74AVC4T245 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVC4T245 device is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC4T245 device is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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技术文档

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类型 项目标题 下载最新的英语版本 日期
* 数据表 SN74AVC4T245 Dual-Bit Bus Transceiver with Configurable Voltage Translation and 3-State Outputs 数据表 (Rev. G) PDF | HTML 2014年 11月 5日
EVM 用户指南 AVCLVCDIRCNTRL-EVM 评估模块 (Rev. B) PDF | HTML 下载英文版本 (Rev.B) 2021年 8月 17日
EVM 用户指南 AXC-SMALLPKG1EVM 评估模块 (Rev. A) 下载英文版本 (Rev.A) PDF | HTML 2021年 7月 29日
选择指南 Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
技术文章 Benefits of using Sub-1 GHz connectivity for grid asset monitoring, protection and control 2020年 5月 28日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
更多文献资料 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
更多文献资料 Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015年 4月 30日
选择指南 逻辑器件指南 2014 (Rev. AA) 下载最新的英文版本 (Rev.AB) 2014年 11月 17日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
更多文献资料 选择正确的电平转换解决方案 (Rev. A) 下载英文版本 (Rev.A) 2006年 3月 23日
更多文献资料 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
更多文献资料 LCD Module Interface Application Clip 2003年 5月 9日
用户指南 AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 2002年 8月 20日
更多文献资料 Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
更多文献资料 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
更多文献资料 Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 1999年 7月 7日
更多文献资料 AVC Logic Family Technology and Applications (Rev. A) 1998年 8月 26日

设计和开发

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评估板

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。

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14-24-NL-LOGIC-EVM — 通用 14 至 24 引脚无铅封装评估模块

Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
用户指南: PDF | HTML
下载英文版本 (Rev.A): PDF | HTML
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评估板

AVCLVCDIRCNTRL-EVM — 适用于方向控制双向转换器件、支持 AVC 和 LVC 的通用 EVM

该通用 EVM 旨在支持 1、2、4 和 8 通道 LVC 和 AVC 方向控制转换器件。它还以相同数量的通道支持总线保持和汽车 Q1 器件。AVC 是低电压转换器件，具有 12mA 的较低驱动强度。LVC 是 1.65 至 5.5V 的较高电压转换器件，具有 32mA 的较高驱动强度。

用户指南: PDF | HTML
下载英文版本 (Rev.B): PDF | HTML
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开发套件

EVMK2GX — 66AK2Gx 1GHz 评估模块

EVMK2GX（也称为“K2G”）1GHz 评估模块 (EVM) 可以让开发人员迅速开始评估 66AK2Gx 处理器系列，并加速音频、工业电机控制、智能电网保护和其他高可靠性实时计算密集型应用的开发。  66AK2Gx 与基于 KeyStone 的现有 SoC 器件类似，可以让 DSP 和 ARM 内核控制系统中的所有内存和外设。此架构有助于最大限度地提高软件灵活性，并可以在其中实现以 DSP 或 ARM 为中心的系统设计。

无论是 Linux 还是 TI-RTOS 操作系统，处理器 SDK 均支持此 EVM，而且此 EVM 采用 USB、PCIe 和千兆位以太网等主要外设。  (...)

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仿真模型

SN74AVC4T245 IBIS Model (Rev. B)

SCEM503B.ZIP (68 KB) - IBIS Model
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封装 引脚数 下载
SOIC (D) 16 了解详情
TSSOP (PW) 16 了解详情
TVSOP (DGV) 16 了解详情
UQFN (RSV) 16 了解详情
VQFN (RGY) 16 了解详情

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  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

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