SN74AUP2G08
- Available in the Texas Instruments NanoStar™ Package
- Low Static-Power Consumption
(ICC = 0.9 µA Max) - Low Dynamic-Power Consumption
(Cpd = 4.3 pF Typ at 3.3 V) - Low Input Capacitance (Ci = 1.5 pF Typ)
- Low Noise – Overshoot and Undershoot
<10% of VCC - Ioff Supports Partial-Power-Down Mode Operation
- Schmitt-Trigger Action Allows Slow Input Transition and
Better Switching Noise Immunity at the Input
(Vhys = 250 mV Typ at 3.3 V) - Wide Operating VCC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
- 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- tpd = 5.9 ns Max at 3.3 V
- Suitable for Point-to-Point Applications
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II) - 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model
NanoStar is a trademark of Texas Instruments.
The AUP family is TIs premier solution to the industrys low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
This dual 2-input positive-AND gate performs the Boolean function Y = A B or Y = A\ + B\ in positive logic.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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技术文档
类型 | 项目标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | SN74AUP2G08 Low-Power Dual 2-Input Positive-AND Gate 数据表 (Rev. C) | 2009年 12月 30日 | |||
应用手册 | 了解施密特触发器 (Rev. A) | PDF | HTML | 下载英文版本 (Rev.A) | PDF | HTML | 2022年 12月 1日 | |
选择指南 | Little Logic Guide 2018 (Rev. G) | 2018年 7月 6日 | ||||
选择指南 | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||||
应用手册 | How to Select Little Logic (Rev. A) | 2016年 7月 26日 | ||||
选择指南 | 逻辑器件指南 2014 (Rev. AA) | 下载最新的英文版本 (Rev.AB) | 2014年 11月 17日 | |||
选择指南 | 小尺寸逻辑器件指南 (Rev. E) | 下载最新的英文版本 (Rev.G) | 2012年 7月 16日 | |||
应用手册 | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 |
设计和开发
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5-8-LOGIC-EVM — 支持 5 至 8 引脚 DCK、DCT、DCU、DRL 和 DBV 封装的通用逻辑 EVM
封装 | 引脚数 | 下载 |
---|---|---|
DSBGA (YFP) | 8 | 了解详情 |
DSBGA (YZP) | 8 | 了解详情 |
UQFN (RSE) | 8 | 了解详情 |
VSSOP (DCU) | 8 | 了解详情 |
X2SON (DQE) | 8 | 了解详情 |
订购和质量
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- 器件标识
- 引脚镀层/焊球材料
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- 材料成分
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