SN74AUP1T32
- Single-Supply Voltage Translator
- Output Level Up to Supply VCC CMOS Level
- 1.8 V to 3.3 V (at VCC = 3.3 V)
- 2.5 V to 3.3 V (at VCC = 3.3 V)
- 1.8 V to 2.5 V (at VCC = 2.5 V)
- 3.3 V to 2.5 V (at VCC = 2.5 V
- Schmitt-Trigger Inputs Reject Input Noise and Provide
Better Output Signal Integrity - Ioff Supports Partial Power Down (VCC = 0 V)
- Very Low Static Power Consumption:
0.1 µA - Very Low Dynamic Power Consumption:
0.9 µA - Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- Pb-Free Packages Available: SC-70 (DCK)
2 × 2.1 × 0.65 mm (Height 1.1 mm) - More Gate Options Available at www.ti.com/littlelogic
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II) - 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model
The SN74AUP1T32 performs the Boolean function Y = A + B or Y = A\ B\ with designation for logic-level translation applications with output referenced to supply VCC.
AUP technology is the industrys lowest-power logic technology designed for use in extending battery-life in operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply. This product also maintains excellent signal integrity (see Figure 1 and Figure 2).
The wide VCC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external controllers or processors.
Schmitt-trigger inputs (VT = 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.
Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions.
The SN74AUP1T32 is designed with optimized current-drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.
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技术文档
类型 | 标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | Low Power, 1.8/2.5/3.3-V Input, 3.3-V CMOS Output, 2-Input Positive-OR Gate 数据表 | 2010年 4月 16日 | |||
应用简报 | 了解施密特触发器 (Rev. A) | PDF | HTML | 英语版 (Rev.A) | PDF | HTML | 2022年 12月 1日 | |
选择指南 | Voltage Translation Buying Guide (Rev. A) | 2021年 4月 15日 | ||||
选择指南 | 逻辑器件指南 2014 (Rev. AA) | 最新英语版本 (Rev.AB) | 2014年 11月 17日 |
设计和开发
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5-8-LOGIC-EVM — 支持 5 至 8 引脚 DCK、DCT、DCU、DRL 和 DBV 封装的通用逻辑评估模块
封装 | 引脚 | CAD 符号、封装和 3D 模型 |
---|---|---|
SOT-SC70 (DCK) | 5 | Ultra Librarian |
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