LMH0031

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具有视频和辅助数据 FIFO 的数字视频解串器/解码器

产品详情

Function Deserializer Supply voltage (V) 2.5, 3.3 Power consumption (mW) 705 Data rate (max) (Mbps) 1485 Control interface Pin/I2C Operating temperature range (°C) 0 to 70
Function Deserializer Supply voltage (V) 2.5, 3.3 Power consumption (mW) 705 Data rate (max) (Mbps) 1485 Control interface Pin/I2C Operating temperature range (°C) 0 to 70
TQFP (PAG) 64 144 mm² 12 x 12
  • SDTV/HDTV Serial Digital Video Standard Compliant
  • Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.483 Gbps and 1.485 Gbps Serial Video Data Rates with Auto-Detection
  • LSB De-Dithering Option
  • Uses Low-Cost 27MHz Crystal or Clock Oscillator Reference
  • Fast VCO Lock Time: < 500 µs at 1.485 Gbps
  • Built-in Self-Test (BIST) and Video Test Pattern Generator (TPG) Patent Applications Made or Pending
  • Automatic EDH/CRC Word and Flag Processing
  • Ancillary Data FIFO with Extensive Packet Handling Options
  • Adjustable, 4-Deep Parallel Output Video Data FIFO
  • Flexible Control and Configuration I/O Port
  • LVCMOS Compatible Control Inputs and Clock and Data Outputs
  • LVDS and ECL-Compatible, Differential, Serial Inputs
  • 3.3V I/O Power Supply and 2.5V Logic Power Supply Operation
  • Low Power: Typically 850mW
  • 64-Pin TQFP Package
  • Commercial Temperature Range 0°C to +70°C

All trademarks are the property of their respective owners.

  • SDTV/HDTV Serial Digital Video Standard Compliant
  • Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.483 Gbps and 1.485 Gbps Serial Video Data Rates with Auto-Detection
  • LSB De-Dithering Option
  • Uses Low-Cost 27MHz Crystal or Clock Oscillator Reference
  • Fast VCO Lock Time: < 500 µs at 1.485 Gbps
  • Built-in Self-Test (BIST) and Video Test Pattern Generator (TPG) Patent Applications Made or Pending
  • Automatic EDH/CRC Word and Flag Processing
  • Ancillary Data FIFO with Extensive Packet Handling Options
  • Adjustable, 4-Deep Parallel Output Video Data FIFO
  • Flexible Control and Configuration I/O Port
  • LVCMOS Compatible Control Inputs and Clock and Data Outputs
  • LVDS and ECL-Compatible, Differential, Serial Inputs
  • 3.3V I/O Power Supply and 2.5V Logic Power Supply Operation
  • Low Power: Typically 850mW
  • 64-Pin TQFP Package
  • Commercial Temperature Range 0°C to +70°C

All trademarks are the property of their respective owners.

The LMH0031 SMPTE 292M / 259M Digital Video Deserializer/Descrambler with Video and Ancillary Data FIFOs is a monolithic integrated circuit that deserializes and decodes SMPTE 292M, 1.485Gbps (or 1.483Gbps) serial component video data, to 20-bit parallel data with a synchronized parallel word-rate clock. It also deserializes and decodes SMPTE 259M, 270Mbps, 360Mbps and SMPTE 344M (proposed) 540Mbps serial component video data, to 10-bit parallel data. Functions performed by the LMH0031 include: clock/data recovery from the serial data, serial-to-parallel data conversion, SMPTE standard data decoding, NRZI-to-NRZ conversion, parallel data clock generation, word framing, CRC and EDH data checking and handling, Ancillary Data extraction and automatic video format determination. The parallel video output features a variable-depth FIFO which can be adjusted to delay the output data up to 4 parallel data clock periods. Ancillary Data may be selectively extracted from the parallel data through the use of masking and control bits in the configuration and control registers and stored in the on-chip FIFO. Reverse LSB dithering is also implemented.

The unique multi-functional I/O port of the LMH0031 provides external access to functions and data stored in the configuration and control registers. This feature allows the designer greater flexibility in tailoring the LMH0031 to the desired application. The LMH0031 is auto-configured to a default operating condition at power-on or after a reset command. Separate power pins for the PLL, deserializer and other functional circuits improve power supply rejection and noise performance.

The LMH0031 has a unique Built-In Self-Test (BIST) and video Test Pattern Generator (TPG). The BIST enables comprehensive testing of the device by the user. The BIST uses the TPG as input data and includes SD and HD component video test patterns, reference black, PLL and EQ pathologicals and a 75% saturation, 8 vertical colour bar pattern, for all implemented rasters. The colour bar pattern has optional transition coding at changes in the chroma and luma bar data. The TPG data is output via the parallel data port.

The LMH0030, SMPTE 292M / 259M Digital Video Serializer with Ancillary Data FIFO and Integrated Cable Driver, is the ideal complement to the LMH0031.

The LMH0031's internal circuitry is powered from +2.5 Volts and the I/O circuitry from a +3.3 Volt supply. Power dissipation is typically 850mW. The device is packaged in a 64-pin TQFP.

The LMH0031 SMPTE 292M / 259M Digital Video Deserializer/Descrambler with Video and Ancillary Data FIFOs is a monolithic integrated circuit that deserializes and decodes SMPTE 292M, 1.485Gbps (or 1.483Gbps) serial component video data, to 20-bit parallel data with a synchronized parallel word-rate clock. It also deserializes and decodes SMPTE 259M, 270Mbps, 360Mbps and SMPTE 344M (proposed) 540Mbps serial component video data, to 10-bit parallel data. Functions performed by the LMH0031 include: clock/data recovery from the serial data, serial-to-parallel data conversion, SMPTE standard data decoding, NRZI-to-NRZ conversion, parallel data clock generation, word framing, CRC and EDH data checking and handling, Ancillary Data extraction and automatic video format determination. The parallel video output features a variable-depth FIFO which can be adjusted to delay the output data up to 4 parallel data clock periods. Ancillary Data may be selectively extracted from the parallel data through the use of masking and control bits in the configuration and control registers and stored in the on-chip FIFO. Reverse LSB dithering is also implemented.

The unique multi-functional I/O port of the LMH0031 provides external access to functions and data stored in the configuration and control registers. This feature allows the designer greater flexibility in tailoring the LMH0031 to the desired application. The LMH0031 is auto-configured to a default operating condition at power-on or after a reset command. Separate power pins for the PLL, deserializer and other functional circuits improve power supply rejection and noise performance.

The LMH0031 has a unique Built-In Self-Test (BIST) and video Test Pattern Generator (TPG). The BIST enables comprehensive testing of the device by the user. The BIST uses the TPG as input data and includes SD and HD component video test patterns, reference black, PLL and EQ pathologicals and a 75% saturation, 8 vertical colour bar pattern, for all implemented rasters. The colour bar pattern has optional transition coding at changes in the chroma and luma bar data. The TPG data is output via the parallel data port.

The LMH0030, SMPTE 292M / 259M Digital Video Serializer with Ancillary Data FIFO and Integrated Cable Driver, is the ideal complement to the LMH0031.

The LMH0031's internal circuitry is powered from +2.5 Volts and the I/O circuitry from a +3.3 Volt supply. Power dissipation is typically 850mW. The device is packaged in a 64-pin TQFP.

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类型 标题 下载最新的英语版本 日期
* 数据表 LMH0031 SMPTE 292M/259M Dig Video Deserial/Descram w/Video & Ancillary Data FIFO 数据表 (Rev. A) 2013年 4月 15日
选择指南 Broadcast and Professional Video Interface Solutions (Rev. E) 2017年 4月 5日
应用手册 AN-1334 The LMH0030 in Segmented Frames Applications (Rev. B) 2013年 4月 26日
应用手册 AN-1336 LMH0030 or LMH0031 Control Port Bussed Operation (Rev. B) 2013年 4月 26日
应用手册 AN-1943 Understanding Serial Digital Video Bit Rates (Rev. A) 2013年 4月 26日
应用手册 AN-2145 Power Considerations for SDI Products (Rev. B) 2013年 4月 26日
应用手册 AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) 2013年 4月 26日
应用手册 Enhancing LMH0031 Jitter Perf w/Easy-To-Use VCXOs (Rev. B) 2013年 4月 26日
应用手册 High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems 2009年 11月 12日
应用手册 LMH0030 (CLC030), LMH0031 (CLC031A) ‚Çô Frequently Asked Questions (FAQs) 2008年 8月 26日
应用手册 Timing is Everything ‚Çô The Broadcast Video Signal Path 2007年 8月 2日
应用手册 Enhancing LMH0031 Jitter Perf w/Easy-To-Use VCXOs (cn) 2006年 8月 3日
应用手册 Application Note 1334 The LMH0030 in Segmented Frames Applications (cn) 2006年 8月 1日
应用手册 Application Note 1336 LMH0030 or LMH0031 Control Port Bussed Operation (cn) 2006年 7月 31日

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英语版 (Rev.A): PDF
封装 引脚 CAD 符号、封装和 3D 模型
TQFP (PAG) 64 Ultra Librarian

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包含信息:
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  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
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