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FPD-Link 串行器/解串器

DS99R124AQ-Q1

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5MHz 至 43MHz 18 位彩色 FPD-Link II 至 FPD-Link 转换器

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数据表

DS99R124AQ-Q1

正在供货
数据表 立即订购

产品详情

Applications In-vehicle Infotainment (IVI) Input compatibility FPD-Link LVDS Function Deserializer Output compatibility FPD-Link LVDS Color depth (bpp) 18 Features I2C Config Signal conditioning Programmable Equalizer EMI reduction LVDS Diagnostics BIST Rating Automotive Operating temperature range (°C) -40 to 105
Applications In-vehicle Infotainment (IVI) Input compatibility FPD-Link LVDS Function Deserializer Output compatibility FPD-Link LVDS Color depth (bpp) 18 Features I2C Config Signal conditioning Programmable Equalizer EMI reduction LVDS Diagnostics BIST Rating Automotive Operating temperature range (°C) -40 to 105
WQFN (RHS) 48 49 mm² (7 mm × 7 mm)
  • 5 – 43 MHz Support (140 Mbps to 1.2 Gbps Serial Link)
  • 4-Channel (3 data + 1 clock) FPD-Link LVDS Outputs
  • 3 Low-Speed Over-Sampled LVCMOS Outputs
  • AC Coupled STP Interconnect up to 10 Meters in Length
  • Integrated Input Termination
  • @ Speed Link BIST Mode and Reporting Pin
  • Optional I2C Compatible Serial Control Bus
  • RGB666 + VS, HS, DE Converted from 1 Pair
  • Power Down Mode Minimizes Power Dissipation
  • FAST Random Data Lock; No Reference Clock Required
  • Adjustable Input Receive Equalization
  • LOCK (Real Time Link Status) Reporting Pin
  • Low EMI FPD-Link Output
  • SSCG Option for Lower EMI
  • 1.8V or 3.3V Compatible I/O Interface
  • Automotive Grade Product: AEC-Q100 Grade 2 Qualified
  • >8 kV HBM and ISO 10605 ESD Rating

All trademarks are the property of their respective owners.

  • 5 – 43 MHz Support (140 Mbps to 1.2 Gbps Serial Link)
  • 4-Channel (3 data + 1 clock) FPD-Link LVDS Outputs
  • 3 Low-Speed Over-Sampled LVCMOS Outputs
  • AC Coupled STP Interconnect up to 10 Meters in Length
  • Integrated Input Termination
  • @ Speed Link BIST Mode and Reporting Pin
  • Optional I2C Compatible Serial Control Bus
  • RGB666 + VS, HS, DE Converted from 1 Pair
  • Power Down Mode Minimizes Power Dissipation
  • FAST Random Data Lock; No Reference Clock Required
  • Adjustable Input Receive Equalization
  • LOCK (Real Time Link Status) Reporting Pin
  • Low EMI FPD-Link Output
  • SSCG Option for Lower EMI
  • 1.8V or 3.3V Compatible I/O Interface
  • Automotive Grade Product: AEC-Q100 Grade 2 Qualified
  • >8 kV HBM and ISO 10605 ESD Rating

All trademarks are the property of their respective owners.

The DS99R124AQ converts FPD-Link II to FPD-Link. It translates a high-speed serialized interface with an embedded clock over a single pair (FPD-Link II) to three LVDS data/control streams and one LVDS clock pair (FPD-Link). This serial bus scheme greatly eases system design by eliminating skew problems between clock and data, reduces the number of connector pins, reduces the interconnect size, weight, and cost, and overall eases PCB layout. In addition, internal DC balanced decoding is used to support AC-coupled interconnects.

The DS99R124AQ converter recovers the data (RGB) and control signals and extracts the clock from a serial stream (FPD-Link II). It is able to lock to the incoming data stream without the use of a training sequence or special SYNC patterns and does not require a reference clock. A link status (LOCK) output signal is provided.

Adjustable input equalization of the serial input stream provides compensation for transmission medium losses of the cable and reduces the medium-induced deterministic jitter. EMI is minimized by the use of low voltage differential signaling, output state select feature, and additional output spread spectrum generation.

With fewer wires to the physical interface of the display, FPD-Link output with LVDS technology is ideal for high speed, low power and low EMI data transfer.

The DS99R124AQ is offered in a 48-pin WQFN package and is specified over the automotive AEC-Q100 Grade 2 temperature range of -40˚C to +105˚C.

The DS99R124AQ converts FPD-Link II to FPD-Link. It translates a high-speed serialized interface with an embedded clock over a single pair (FPD-Link II) to three LVDS data/control streams and one LVDS clock pair (FPD-Link). This serial bus scheme greatly eases system design by eliminating skew problems between clock and data, reduces the number of connector pins, reduces the interconnect size, weight, and cost, and overall eases PCB layout. In addition, internal DC balanced decoding is used to support AC-coupled interconnects.

The DS99R124AQ converter recovers the data (RGB) and control signals and extracts the clock from a serial stream (FPD-Link II). It is able to lock to the incoming data stream without the use of a training sequence or special SYNC patterns and does not require a reference clock. A link status (LOCK) output signal is provided.

Adjustable input equalization of the serial input stream provides compensation for transmission medium losses of the cable and reduces the medium-induced deterministic jitter. EMI is minimized by the use of low voltage differential signaling, output state select feature, and additional output spread spectrum generation.

With fewer wires to the physical interface of the display, FPD-Link output with LVDS technology is ideal for high speed, low power and low EMI data transfer.

The DS99R124AQ is offered in a 48-pin WQFN package and is specified over the automotive AEC-Q100 Grade 2 temperature range of -40˚C to +105˚C.
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* 数据表 DS99R124AQ 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter 数据表 (Rev. A) 2013-4-16

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封装 引脚 CAD 符号、封装和 3D 模型
WQFN (RHS) 48 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

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