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DS99R103

已停产

适用于 -40°C 至 85°C 的 3MHz 至 40MHz 直流平衡 24 位 LVDS 串行器

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数据表

DS99R103

已停产
数据表 立即订购

产品详情

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
WQFN (NJU) 48 49 mm² 7 x 7
  • 3 MHz–40 MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
  • Capable to Drive Shielded Twisted-Pair Cable
  • User Selectable Clock Edge for Parallel Data on both Transmitter and Receiver
  • Internal DC Balancing Encode/Decode – Supports AC-Coupling Interface with no External Coding Required
  • Individual Power-Down Controls for both Transmitter and Receiver
  • Embedded Clock CDR (Clock and Data Recovery) on Receiver and no External Source of Reference Clock Needed
  • All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
  • LOCK Output Flag to Ensure Data Integrity at Receiver Side
  • Balanced TSETUP/THOLD Between RCLK and RDATA on Receiver Side
  • PTO (Progressive Turn-On) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
  • All LVCMOS inputs and control pins have internal pulldown
  • On-Chip Filters for PLLs on Transmitter and Receiver
  • Integrated 100Ω Input Termination on Receiver
  • 4 mA Receiver Output Drive
  • 48-Pin TQFP and 48-Pin WQFN Packages
  • Pure CMOS .35 μm Process
  • Power Supply Range 3.3V ± 10%
  • Temperature Range −40°C to +85°C
  • 8 kV HBM ESD Tolerance

All trademarks are the property of their respective owners.

  • 3 MHz–40 MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
  • Capable to Drive Shielded Twisted-Pair Cable
  • User Selectable Clock Edge for Parallel Data on both Transmitter and Receiver
  • Internal DC Balancing Encode/Decode – Supports AC-Coupling Interface with no External Coding Required
  • Individual Power-Down Controls for both Transmitter and Receiver
  • Embedded Clock CDR (Clock and Data Recovery) on Receiver and no External Source of Reference Clock Needed
  • All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
  • LOCK Output Flag to Ensure Data Integrity at Receiver Side
  • Balanced TSETUP/THOLD Between RCLK and RDATA on Receiver Side
  • PTO (Progressive Turn-On) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
  • All LVCMOS inputs and control pins have internal pulldown
  • On-Chip Filters for PLLs on Transmitter and Receiver
  • Integrated 100Ω Input Termination on Receiver
  • 4 mA Receiver Output Drive
  • 48-Pin TQFP and 48-Pin WQFN Packages
  • Pure CMOS .35 μm Process
  • Power Supply Range 3.3V ± 10%
  • Temperature Range −40°C to +85°C
  • 8 kV HBM ESD Tolerance

All trademarks are the property of their respective owners.

The DS99R103/DS99R104 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS99R103/DS99R104 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced.

In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.

The DS99R103/DS99R104 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS99R103/DS99R104 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced.

In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
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类型 标题 下载最新的英语版本 日期
* 数据表 DS99R103/DS99R104 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer 数据表 (Rev. D) 2013年 4月 16日

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点