FunctionSerializerColor depth (bpp)18Pixel clock min (MHz)3Pixel clock (Max) (MHz)40Input compatibilityLVCMOSOutput compatibilityFPD-Link LVDSFeaturesCapable to Drive Shielded Twisted-Pair Cable, Embedded Clock CDR, LOCK Output Flag, All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications, User Selectable Clock Edge for Parallel DataSignal conditioningPre-EmphasisEMI reductionProgressive Turn On (PTO), LVDS OutputsDiagnostics—Total throughput (Mbps)960RatingCatalogOperating temperature range (C)-40 to 85open-in-new查找其它 显示 SerDes
The DS99R103/DS99R104 Chipset translates a 24-bit parallel bus into a fully transparent
data/control LVDS serial stream with embedded clock information. This single serial stream
simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems
between parallel data and clock paths. It saves system cost by narrowing data paths that in turn
reduce PCB layers, cable width, and connector size and pins.
The DS99R103/DS99R104 incorporates LVDS signaling on the high-speed I/O. LVDS provides a
low power and low noise environment for reliably transferring data over a serial transmission path.
By optimizing the serializer output edge rate for the operating frequency range EMI is further
In addition the device features pre-emphasis to boost signals over longer distances using
lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled