封装信息
| 封装 | 引脚 TQFP (PAG) | 64 |
| 工作温度范围 (°C) -40 to 85 |
| 包装数量 | 包装 160 | JEDEC TRAY (10+1) |
DS92LV3222 的特性
- Wide Operating Range Embedded
Clock SER/DES
- Up to 32-bit Parallel LVCMOS Data
- 20 to 50 MHz Parallel Clock
- Up to 1.6 Gbps Application Data Paylod
- Simplified Clocking
Architecture
- No Separate Serial Clock Line
- No Reference Clock Required
- Receiver Locks to Random Data
- On-chip Signal Conditioning for Robust Serial
Connectivity
- Transmit Pre-Emphasis
- Data Randomization
- DC-Balance Encoding
- Receive Channel Deskew
- Supports up to 10m CAT-5 at 1.6Gbps
- Integrated LVDS Terminations
- Built-in AT-SPEED BIST for End-To-End System Testing
- AC-Coupled Interconnect for Isolation and Fault Protection
- > 4KV HBM ESD Protection
- Space-Saving 64-pin TQFP Package
- Full Industrial Temperature Range: -40° to +85°C
All trademarks are the property of their respective owners.
DS92LV3222 的说明
The DS92LV3221 (SER) serializes a 32-bit data bus into 2 embedded clock LVDS serial channels for a data payload rate up to 1.6 Gbps over cables such as CATx, or backplanes FR-4 traces. The companion DS92LV3222 (DES) deserializes the 2 LVDS serial data channels, de-skews channel-to-channel delay variations and converts the LVDS data stream back into a 32-bit LVCMOS parallel data bus.
On-chip data Randomization/Scrambling and DC balance encoding and selectable serializer Pre-emphasis ensure a robust, low-EMI transmission over longer, lossy cables and backplanes. The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing an easy “plug-and-lock” operation.
By embedding the clock in the data payload and including signal conditioning functions, the Channel-Link II SerDes devices reduce trace count, eliminate skew issues, simplify design effort and lower cable/connector cost for a wide variety of video, control and imaging applications. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics.