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LVDS、M-LVDS 和 PECL IC

DS91D176

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100MHz 单通道 M-LVDS 收发器

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数据表

DS91D176

正在供货
数据表 立即订购

产品详情

Function Transceiver Protocols M-LVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 200 Input signal LVTTL, M-LVDS Output signal LVTTL, M-LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Transceiver Protocols M-LVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 200 Input signal LVTTL, M-LVDS Output signal LVTTL, M-LVDS Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² 4.9 x 6
  • DC to 100+ MHz / 200+ Mbps Low Power, Low EMI Operation
  • Optimal for ATCA, uTCA Clock Distribution Networks
  • Meets or Exceeds TIA/EIA-899 M-LVDS Standard
  • Wide Input Common Mode Voltage for Increased Noise Immunity
  • DS91D176 has Type 1 Receiver Input
  • DS91C176 has Type 2 Receiver with Fail-safe
  • Industrial Temperature Range
  • Space Saving SOIC-8 Package

All trademarks are the property of their respective owners.

  • DC to 100+ MHz / 200+ Mbps Low Power, Low EMI Operation
  • Optimal for ATCA, uTCA Clock Distribution Networks
  • Meets or Exceeds TIA/EIA-899 M-LVDS Standard
  • Wide Input Common Mode Voltage for Increased Noise Immunity
  • DS91D176 has Type 1 Receiver Input
  • DS91C176 has Type 2 Receiver with Fail-safe
  • Industrial Temperature Range
  • Space Saving SOIC-8 Package

All trademarks are the property of their respective owners.

The DS91C176 and DS91D176 are 100 MHz single channel M-LVDS (Multipoint Low Voltage Differential Signaling) transceivers designed for applications that utilize multipoint networks (e.g. clock distribution in ATCA and uTCA based systems). M-LVDS is a new bus interface standard (TIA/EIA-899) optimized for multidrop networks. Controlled edge rates, tight input receiver thresholds and increased drive strength are sone of the key enhancements that make M-LVDS devices an ideal choice for distributing signals via multipoint networks.

The DS91C176/DS91D176 are half-duplex transceivers that accept LVTTL/LVCMOS signals at the driver inputs and convert them to differential M-LVDS signals. The receiver inputs accept low voltage differential signals (LVDS, B-LVDS, M-LVDS, LV-PECL and CML) and convert them to 3V LVCMOS signals. The DS91D176 has a M-LVDS type 1 receiver input with no offset. The DS91C176 has an M-LVDS type 2 receiver which enable failsafe functionality.

The DS91C176 and DS91D176 are 100 MHz single channel M-LVDS (Multipoint Low Voltage Differential Signaling) transceivers designed for applications that utilize multipoint networks (e.g. clock distribution in ATCA and uTCA based systems). M-LVDS is a new bus interface standard (TIA/EIA-899) optimized for multidrop networks. Controlled edge rates, tight input receiver thresholds and increased drive strength are sone of the key enhancements that make M-LVDS devices an ideal choice for distributing signals via multipoint networks.

The DS91C176/DS91D176 are half-duplex transceivers that accept LVTTL/LVCMOS signals at the driver inputs and convert them to differential M-LVDS signals. The receiver inputs accept low voltage differential signals (LVDS, B-LVDS, M-LVDS, LV-PECL and CML) and convert them to 3V LVCMOS signals. The DS91D176 has a M-LVDS type 1 receiver input with no offset. The DS91C176 has an M-LVDS type 2 receiver which enable failsafe functionality.
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技术文档

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类型 标题 下载最新的英语版本 日期
* 数据表 DS91D176/DS91C176 100 MHz Single Channel M-LVDS Transceivers 数据表 (Rev. L) 2013年 4月 16日
应用简报 How Far, How Fast Can You Operate MLVDS? 2018年 8月 6日
应用手册 Designing an ATCA Compliant M-LVDS Clock Distribution Network (Rev. B) 2013年 4月 26日
应用手册 Introduction to M-LVDS (TIA/EIA-899) (Rev. A) 2013年 1月 3日
EVM 用户指南 100 MHz M-LVDS Transceiver Evaluation Board 2012年 1月 26日
应用手册 Designing an ATCA Compliant M-LVDS Clock Distribution Network (cn) 2007年 11月 20日

设计和开发

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仿真模型

DS91D176 IBIS Model

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  • 器件标识
  • 引脚镀层/焊球材料
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