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DS100KR401

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具有 EQ 和 DE 功能的 10.3Gbps 4 路(8 通道)转接驱动器

产品详情

Type Redriver Number of channels 8 Input compatibility AC-coupling, CML Speed (max) (Gbps) 10.3 Protocols 10G-KR, 10G-SR/LR, 40G-KR4, 40G-SR4/LR4, CPRI, Fibre Channel, General purpose, Infiniband, Interlaken, OBSAI, sRIO Operating temperature range (°C) -40 to 85
Type Redriver Number of channels 8 Input compatibility AC-coupling, CML Speed (max) (Gbps) 10.3 Protocols 10G-KR, 10G-SR/LR, 40G-KR4, 40G-SR4/LR4, CPRI, Fibre Channel, General purpose, Infiniband, Interlaken, OBSAI, sRIO Operating temperature range (°C) -40 to 85
WQFN (NJY) 54 55 mm² 10 x 5.5

  • Comprehensive product family:

  • DS100KR800: 8-channel, uni-directional repeater

  • DS100KR401: 4x lane, bi-directional repeater

  • DS100BR210: 2-channel, uni-directional repeater

  • DS100BR111: 1x lane, bi-directional repeater
  • 4 lane (8-channel, bi-directional) repeater for 4x 10G-KR and other serial standards up to 10.3 Gbps
  • Transparent management of 10G-KR (802.3ap) link training protocol
  • Low 65 mW/channel (typ) power consumption, with option to power down unused channels
  • Advanced signal conditioning features

  • - Receive Equalization up to 36 dB at 5 GHz

  • - Transmit de-emphasis up to -12 dB

  • - Transmit output voltage control: 700 mV to 1300 mV
  • Programmable via pin selection, EEPROM or SMBus interface
  • Single supply operation selectable: 2.5V or 3.3V
  • -40˚ to +85˚C operating temperature range
  • 3 kV HBM ESD rating
  • Flow-thru pinout in 10mmx5.5mm 54-pin leadless LLP package

  • Comprehensive product family:

  • DS100KR800: 8-channel, uni-directional repeater

  • DS100KR401: 4x lane, bi-directional repeater

  • DS100BR210: 2-channel, uni-directional repeater

  • DS100BR111: 1x lane, bi-directional repeater
  • 4 lane (8-channel, bi-directional) repeater for 4x 10G-KR and other serial standards up to 10.3 Gbps
  • Transparent management of 10G-KR (802.3ap) link training protocol
  • Low 65 mW/channel (typ) power consumption, with option to power down unused channels
  • Advanced signal conditioning features

  • - Receive Equalization up to 36 dB at 5 GHz

  • - Transmit de-emphasis up to -12 dB

  • - Transmit output voltage control: 700 mV to 1300 mV
  • Programmable via pin selection, EEPROM or SMBus interface
  • Single supply operation selectable: 2.5V or 3.3V
  • -40˚ to +85˚C operating temperature range
  • 3 kV HBM ESD rating
  • Flow-thru pinout in 10mmx5.5mm 54-pin leadless LLP package

  • The DS100KR401 is an extremely low power, high performance repeater designed to support 4 lane (bi-directional) 10G-KR and other high speed interface serial protocols up to 10.3 Gbps. The receiver's continuous time linear equalizer (CTLE) provides a boost of up to +36 dB at 5 GHz (10.3125 Gbps) in each of its eight channels and is capable of opening an input eye that is completely closed due to inter symbol interference (ISI) induced by interconnect medium such as long backplanes or cables, hence enabling host controllers to ensure an error free end-to-end link. The transmitter provides a de-emphasis boost of up to -12 dB and output voltage amplitude control from 700 mV to 1300 mV to allow maximum flexibility in the physical placement within the interconnect channel.

    When operating in 10G-KR mode, the DS100KR401 transparently allows the host controller and the end point to optimize the full link and negotiate transmit equalizer coefficients as defined in the 802.3ap standard. This seamless management of the link training protocol ensures guaranteed system level interoperability with minimum latency.

    With a low power consumption of 65 mW/channel (typ) and option to turn-off unused channels, the DS100KR401 enables energy efficient system design. A single supply of 3.3v or 2.5v is required to power the device.

    The programmable settings can be applied via pin settings, SMBus (I2C) protocol or an external EEPROM. When operating in the EEPROM mode, the configuration information is automatically loaded on power up. This eliminates the need for an external microprocessor or software driver.


    The DS100KR401 is an extremely low power, high performance repeater designed to support 4 lane (bi-directional) 10G-KR and other high speed interface serial protocols up to 10.3 Gbps. The receiver's continuous time linear equalizer (CTLE) provides a boost of up to +36 dB at 5 GHz (10.3125 Gbps) in each of its eight channels and is capable of opening an input eye that is completely closed due to inter symbol interference (ISI) induced by interconnect medium such as long backplanes or cables, hence enabling host controllers to ensure an error free end-to-end link. The transmitter provides a de-emphasis boost of up to -12 dB and output voltage amplitude control from 700 mV to 1300 mV to allow maximum flexibility in the physical placement within the interconnect channel.

    When operating in 10G-KR mode, the DS100KR401 transparently allows the host controller and the end point to optimize the full link and negotiate transmit equalizer coefficients as defined in the 802.3ap standard. This seamless management of the link training protocol ensures guaranteed system level interoperability with minimum latency.

    With a low power consumption of 65 mW/channel (typ) and option to turn-off unused channels, the DS100KR401 enables energy efficient system design. A single supply of 3.3v or 2.5v is required to power the device.

    The programmable settings can be applied via pin settings, SMBus (I2C) protocol or an external EEPROM. When operating in the EEPROM mode, the configuration information is automatically loaded on power up. This eliminates the need for an external microprocessor or software driver.


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    类型 标题 下载最新的英语版本 日期
    * 数据表 DS100KR401 Ultra Low Power 4 Lane Advanced Repeater for 10G-KR 数据表 (Rev. B) 2012年 3月 22日
    应用手册 利用适用于 10G 至 12.5G 应用的以太网转接驱动器和重定时器来扩大覆盖范围 (Rev. A) PDF | HTML 英语版 (Rev.A) 2023年 2月 12日
    应用手册 Understanding EEPROM Programming for High Speed Repeaters and Mux Buffers 2014年 10月 9日
    用户指南 DS100KR401EVK User's Guide: 4 Channels SMA Evaluation Kit 2013年 10月 25日
    设计指南 适用于 Xilinx FPGA 的模拟器件 解决方案指南 2012年 4月 24日

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