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CDCVF310

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适用于通用应用且支持高达 85°C 温度的高性能 1:10 时钟缓冲器

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CDCVF310

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产品详情

Function Single-ended Additive RMS jitter (typ) (fs) 40 Output frequency (max) (MHz) 200 Number of outputs 10 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 100 Features Pin control Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVTTL Input type LVTTL
Function Single-ended Additive RMS jitter (typ) (fs) 40 Output frequency (max) (MHz) 200 Number of outputs 10 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 100 Features Pin control Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVTTL Input type LVTTL
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • High-Performance 1:10 Clock Driver
  • Pin-to-Pin Skew < 100 ps at VDD 3.3 V
  • VDD Range = 2.3 V to 3.6 V
  • Input Clock Up To 200 MHz (See Figure 7)
  • Operating Temperature Range -40°C to 85°C
  • Output Enable Glitch Suppression
  • Distributes One Clock Input to Two Banks of Five Outputs
  • Packaged in 24-Pin TSSOP
  • Pin-to-Pin Compatible to the CDCVF2310,
    Except the R = 22- Series Damping
    Resistors at Yn
  • APPLICATIONS
    • General-Purpose Applications
  • High-Performance 1:10 Clock Driver
  • Pin-to-Pin Skew < 100 ps at VDD 3.3 V
  • VDD Range = 2.3 V to 3.6 V
  • Input Clock Up To 200 MHz (See Figure 7)
  • Operating Temperature Range -40°C to 85°C
  • Output Enable Glitch Suppression
  • Distributes One Clock Input to Two Banks of Five Outputs
  • Packaged in 24-Pin TSSOP
  • Pin-to-Pin Compatible to the CDCVF2310,
    Except the R = 22- Series Damping
    Resistors at Yn
  • APPLICATIONS
    • General-Purpose Applications

The CDCVF310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.

The CDCVF310 is characterized for operation from -40°C to 85°C.

The CDCVF310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.

The CDCVF310 is characterized for operation from -40°C to 85°C.
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* 数据表 2.5-V to 3.3-V High-Performance Clock Buffer 数据表 (Rev. B) 2008年 1月 22日

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仿真模型

CDCVF310 IBIS Model (Rev. A)

SCAC058A.ZIP (22 KB) - IBIS Model
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TSSOP (PW) 24 查看选项
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订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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