The CDCM61004 is a highly versatile, low-jitter frequency synthesizer capable of
generating four low-jitter clock outputs, selectable between low-voltage positive emitter coupled
logic (LVPECL), low-voltage differential signaling (LVDS), or low-voltage complementary metal oxide
semiconductor (LVCMOS) outputs, from a low-frequency crystal of LVCMOS input for a variety of
wireline and data communication applications. The CDCM61004 features an onboard PLL that can be
easily configured solely through control pins. The overall output random jitter performance is less
than 1 ps, RMS (from 10 kHz to 20 MHz), making this device a perfect choice for use in demanding
applications such as SONET, Ethernet, Fibre Channel, and SAN. The CDCM61004 is available in a
small, 32-pin, 5-mm × 5-mm VQFN package.
The CDCM61004 is a high-performance, low-phase noise, fully-integrated voltage-controlled
oscillator (VCO) clock synthesizer with four universal output buffers that can be configured to be
LVPECL, LVDS, or LVCMOS compatible. Each universal output can also be converted to two LVCMOS
outputs. Additionally, an LVCMOS bypass output clock is available in an output configuration which
can help with crystal loading to achieve an exact desired input frequency. It has one
fully-integrated, low-noise, LC-based VCO that operates in the
1.75 GHz to 2.05 GHz range.
The phase-locked loop (PLL) synchronizes the VCO with respect to the input, which can
either be a low-frequency crystal. The output share an output divider sourced from the VCO core.
All device settings are managed through a control pin structure, which has two pins that control
the prescaler and feedback divider, three pins that control the output divider, two pins that
control the output type, and one pin that controls the output enable. Any time the PLL settings
(including the input frequency, prescaler divider, or feedback divider) are altered, a reset must
be issued through the Reset control pin (active low for device reset). The reset initiates a PLL
recalibration process to ensure PLL lock. When the device is in reset, the outputs and dividers are
The output frequency (fOUT) is proportional to the frequency of
the input clock (fIN). The feedback divider, output divider, and VCO
frequency set fOUT with respect to fIN.
The output divider can be chosen from 1, 2, 3, 4, 6, or 8 through the use of control
pins. Feedback divider and prescaler divider combinations can be chosen from 25 and 3, 24 and 3, 20
and 4, or 15 and 5, respectively, also through the use of control pins. CDCM61004 Block Diagram shows a high-level diagram of the CDCM61004.
The device operates in a 3.3-V supply environment and is characterized for operation from
40°C to 85°C.