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时钟和计时
时钟缓冲器

CDCFR83

不推荐用于新设计

533MHz Direct Rambus™ 时钟发生器

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CDCFR83 不推荐用于新设计
虽然我们会继续生产此产品供先前的设计使用，但不推荐在新设计中使用此产品。请考虑从这些替代产品中选择一款：
open-in-new 比较替代产品
功能优于比较器件，可直接替换
CDCFR83A 正在供货 Direct Rambus™ 时钟发生器 This device is an updated revision.
功能与比较器件相似
CDCDB2000 正在供货 符合 DB2000QL 标准、适用于第 1 代到第 5 代 PCIe® 的 20 路输出时钟缓冲器 Replacement

CDCFR83

不推荐用于新设计
数据表 立即订购

产品详情

Function Memory interface Output frequency (max) (MHz) 533 Number of outputs 1 Core supply voltage (V) 3.3 Operating temperature range (°C) -40 to 85 Rating Catalog
Function Memory interface Output frequency (max) (MHz) 533 Number of outputs 1 Core supply voltage (V) 3.3 Operating temperature range (°C) -40 to 85 Rating Catalog
SSOP (DBQ) 24 51.9 mm² 8.65 x 6
  • 533-MHz Differential Clock Source for Direct Rambus™ Memory Systems for an 1066-MHz Data Transfer Rate
  • Synchronizes the Clock Domains of the Rambus Channel With an External System or Processor Clock
  • Three Power Operating Modes to Minimize Power for Mobile and Other Power-Sensitive Applications
  • Operates From a Single 3.3-V Supply and 120 mW at 300 MHz (Typ)
  • Packaged in a Shrink Small-Outline Package (DBQ)
  • Supports Frequency Multipliers: 4, 6, 8, 16/3
  • No External Components Required for PLL
  • Supports Independent Channel Clocking
  • Spread Spectrum Clocking Tracking Capability to Reduce EMI
  • Designed for Use With TI’s 133-MHz Clock Synthesizers CDC924 and CDC921
  • Cycle-Cycle Jitter Is Less Than 40 ps at 533 MHz
  • Certified by Gigatest Labs to Exceed the Rambus DRCG Validation Requirement
  • Supports Industrial Temperature Range of –40°C to 85°C

Direct Rambus and Rambus are trademarks of Rambus Inc.

NOT RECOMMENDED FOR NEW DESIGNS USE CDCFR83A AS A REPLACEMENT
  • 533-MHz Differential Clock Source for Direct Rambus™ Memory Systems for an 1066-MHz Data Transfer Rate
  • Synchronizes the Clock Domains of the Rambus Channel With an External System or Processor Clock
  • Three Power Operating Modes to Minimize Power for Mobile and Other Power-Sensitive Applications
  • Operates From a Single 3.3-V Supply and 120 mW at 300 MHz (Typ)
  • Packaged in a Shrink Small-Outline Package (DBQ)
  • Supports Frequency Multipliers: 4, 6, 8, 16/3
  • No External Components Required for PLL
  • Supports Independent Channel Clocking
  • Spread Spectrum Clocking Tracking Capability to Reduce EMI
  • Designed for Use With TI’s 133-MHz Clock Synthesizers CDC924 and CDC921
  • Cycle-Cycle Jitter Is Less Than 40 ps at 533 MHz
  • Certified by Gigatest Labs to Exceed the Rambus DRCG Validation Requirement
  • Supports Industrial Temperature Range of –40°C to 85°C

Direct Rambus and Rambus are trademarks of Rambus Inc.

NOT RECOMMENDED FOR NEW DESIGNS USE CDCFR83A AS A REPLACEMENT

The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system or processor clock. It is designed to support Direct Rambus memory on a desktop, workstation, server, and mobile PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus memory applications.

The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to enable synchronous communication between the Rambus channel and ASIC clock domains. In a Direct Rambus memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the DRCG and memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK to RDRAMs and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK frequencies by ratios M and N such that PCLKM = SYNCLKN, where SYNCLK = BUSCLK/4. The DRCG detects the phase difference between PCLKM and SYNCLKN and adjusts the phase of BUSCLK such that the skew between PCLKM and SYNCLKN is minimized. This allows data to be transferred across the SYNCLK/PCLK boundary without incurring additional latency.

User control is provided by multiply and mode selection terminals. The multiply terminals provide selection of one of four clock frequency multiply ratios, generating BUSCLK frequencies ranging from 267 MHz to 533 MHz with clock references ranging from 33 MHz to 100 MHz. The mode select terminals can be used to select a bypass mode where the frequency multiplied reference clock is directly output to the Rambus channel for systems where synchronization between the Rambus clock and a system clock is not required. Test modes are provided to bypass the PLL and output REFCLK on the Rambus channel and to place the outputs in a high-impedance state for board testing.

The CDCFR83 is characterized for operation over free-air temperatures of –40°C to 85°C.

The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system or processor clock. It is designed to support Direct Rambus memory on a desktop, workstation, server, and mobile PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus memory applications.

The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to enable synchronous communication between the Rambus channel and ASIC clock domains. In a Direct Rambus memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the DRCG and memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK to RDRAMs and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK frequencies by ratios M and N such that PCLKM = SYNCLKN, where SYNCLK = BUSCLK/4. The DRCG detects the phase difference between PCLKM and SYNCLKN and adjusts the phase of BUSCLK such that the skew between PCLKM and SYNCLKN is minimized. This allows data to be transferred across the SYNCLK/PCLK boundary without incurring additional latency.

User control is provided by multiply and mode selection terminals. The multiply terminals provide selection of one of four clock frequency multiply ratios, generating BUSCLK frequencies ranging from 267 MHz to 533 MHz with clock references ranging from 33 MHz to 100 MHz. The mode select terminals can be used to select a bypass mode where the frequency multiplied reference clock is directly output to the Rambus channel for systems where synchronization between the Rambus clock and a system clock is not required. Test modes are provided to bypass the PLL and output REFCLK on the Rambus channel and to place the outputs in a high-impedance state for board testing.

The CDCFR83 is characterized for operation over free-air temperatures of –40°C to 85°C.
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类型 标题 下载最新的英语版本 日期
* 数据表 Direct Rambus Clock Generator 数据表 (Rev. B) 2005年 10月 11日
应用手册 General Application Setup for CDCR83/CDCFR83 2002年 1月 10日

设计和开发

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仿真模型

CDCFR83 IBIS Model (Rev. A)

SCAC022A.ZIP (12 KB) - IBIS Model
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模拟工具

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订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训

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